Intel CORE 2 DUO E4000 - SPECIFICATION UPDATE 3-2008 Specification page 29

Errata
Workaround: Operating systems should not allow A20M# to be enabled if the masking of
address bit 20 could be applied to an address that references a large page.
A20M# is normally only used with the first megabyte of memory.
For the steppings affected, see the Summary Tables of Changes.
Status:
AI18. Writing Shared Unaligned Data that Crosses a Cache Line without
Proper Semaphores or Barriers May Expose a Memory Ordering Issue
Software which is written so that multiple agents can modify the same shared
Problem:
unaligned memory location at the same time may experience a memory
ordering issue if multiple loads access this shared data shortly thereafter.
Exposure to this problem requires the use of a data write which spans a
cache line boundary.
Implication: This erratum may cause loads to be observed out of order. Intel has not
observed this erratum with any commercially available software or system.
Workaround: Software should ensure at least one of the following is true when modifying
shared data by multiple agents:
• The shared data is aligned
• Proper semaphores or barriers are used in order to prevent concurrent data
accesses.
For the steppings affected, see the Summary Tables of Changes.
Status:
AI19. Code Segment Limit Violation May Occur on 4 Gigabyte Limit Check
Code Segment limit violation may occur on 4 Gigabyte limit check when the
Problem:
code stream wraps around in a way that one instruction ends at the last byte
of the segment and the next instruction begins at 0x0.
Implication: This is a rare condition that may result in a system hang. Intel has not
observed this erratum with any commercially available software, or system.
Workaround: Avoid code that wraps around segment limit.
For the steppings affected, see the Summary Tables of Changes.
Status:
AI20. FP Inexact-Result Exception Flag May Not Be Set
When the result of a floating-point operation is not exactly representable in
Problem:
the destination format (1/3 in binary form, for example), an inexact-result
(precision) exception occurs. When this occurs, the PE bit (bit 5 of the FPU
status word) is normally set by the processor. Under certain rare conditions,
this bit may not be set when this rounding occurs. However, other actions
taken by the processor (invoking the software exception handler if the
exception is unmasked) are not affected. This erratum can only occur if one
of the following FST instructions is one or two instructions after the floating-
point operation which causes the precision exception:
• FST m32real
®
Intel Core™2 Extreme Processor X6800 and
®
Intel Core™2 Duo Desktop Processor E6000 and E4000 Sequence
Specification Update
29