Intel CORE 2 DUO E4000 - SPECIFICATION UPDATE 3-2008 Specification page 36

Implication: After an MCE event, accesses to the IA32_APERF and IA32_MPERF MSRs may
return incorrect data. A subsequent reset will clear this condition.
Workaround: None identified.
For the steppings affected, see the Summary Tables of Changes.
Status:
AI35. Incorrect Address Computed For Last Byte of FXSAVE/FXRSTOR
Image Leads to Partial Memory Update
A partial memory state save of the 512-byte FXSAVE image or a partial
Problem:
memory state restore of the FXRSTOR image may occur if a memory address
exceeds the 64KB limit while the processor is operating in 16-bit mode or if a
memory address exceeds the 4GB limit while the processor is operating in
32-bit mode.
Implication: FXSAVE/FXRSTOR will incur a #GP fault due to the memory limit violation as
expected but the memory state may be only partially saved or restored.
Workaround: Software should avoid memory accesses that wrap around the respective 16-
bit and 32-bit mode memory limits.
For the steppings affected, see the Summary Tables of Changes.
Status:
AI36. Split Locked Stores May not Trigger the Monitoring Hardware
Logical processors normally resume program execution following the MWAIT,
Problem:
when another logical processor performs a write access to a WB cacheable
address within the address range used to perform the MONITOR operation.
Due to this erratum, a logical processor may not resume execution until the
next targeted interrupt event or O/S timer tick following a locked store that
spans across cache lines within the monitored address range.
Implication: The logical processor that executed the MWAIT instruction may not resume
execution until the next targeted interrupt event or O/S timer tick in the case
where the monitored address is written by a locked store which is split across
cache lines.
Workaround: Do not use locked stores that span cache lines in the monitored address
range.
For the steppings affected, see the Summary Tables of Changes.
Status:
AI37. REP CMPS/SCAS Operations May Terminate Early in 64-bit Mode
when RCX >= 0X100000000
REP CMPS (Compare String) and SCAS (Scan String) instructions in 64-bit
Problem:
mode may terminate before the count in RCX reaches zero if the initial value
of RCX is greater than or equal to 0X100000000.
Implication: Early termination of REP CMPS/SCAS operation may be observed and RFLAGS
may be incorrectly updated.
36 Intel
Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence
®
Core™2 Extreme Processor X6800 and
Specification Update
Errata