Intel CORE 2 DUO E4000 - SPECIFICATION UPDATE 3-2008 Specification page 46

accessing a page that is scheduled to have its page permissions tightened or
have a page fault handler that ignores any incorrect state.
For the steppings affected, see the Summary Tables of Changes.
Status:
AI63. LBR, BTS, BTM May Report a Wrong Address when an
Exception/Interrupt Occurs in 64-bit Mode
An exception/interrupt event should be transparent to the LBR (Last Branch
Problem:
Record), BTS (Branch Trace Store) and BTM (Branch Trace Message)
mechanisms. However, during a specific boundary condition where the
exception/interrupt occurs right after the execution of an instruction at the
lower canonical boundary (0x00007FFFFFFFFFFF) in 64-bit mode, the LBR
return registers will save a wrong return address with bits 63 to 48
incorrectly sign extended to all 1's. Subsequent BTS and BTM operations
which report the LBR will also be incorrect.
Implication: LBR, BTS and BTM may report incorrect information in the event of an
exception/interrupt.
Workaround: None identified.
For the steppings affected, see the Summary Tables of Changes.
Status:
AI64. Returning to Real Mode from SMM with EFLAGS.VM Set May Result in
Unpredictable System Behavior
Returning back from SMM mode into real mode while EFLAGS.VM is set in
Problem:
SMRAM may result in unpredictable system behavior.
Implication: If SMM software changes the values of the EFLAGS.VM in SMRAM, it may
result in unpredictable system behavior. Intel has not observed this behavior
in commercially available software.
Workaround: SMM software should not change the value of EFLAGS.VM in SMRAM.
For the steppings affected, see the Summary Tables of Changes.
Status:
AI65. A Thermal Interrupt is Not Generated when the Current Temperature
is Invalid
When the DTS (Digital Thermal Sensor) crosses one of its programmed
Problem:
thresholds it generates an interrupt and logs the event
(IA32_THERM_STATUS MSR (019Ch) bits [9,7]). Due to this erratum, if the
DTS reaches an invalid temperature (as indicated IA32_THERM_STATUS MSR
bit[31]) it does not generate an interrupt even if one of the programmed
thresholds is crossed and the corresponding log bits become set.
Implication: When the temperature reaches an invalid temperature the CPU does not
generate a Thermal interrupt even if a programmed threshold is crossed.
Workaround: None identified.
46 Intel
Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence
®
Core™2 Extreme Processor X6800 and
Specification Update
Errata