Intel CORE 2 DUO E4000 - SPECIFICATION UPDATE 3-2008 Specification page 10

Intel® Core™2 Duo/Solo processor for Intel® Centrino® Duo processor
AH =
technology
Intel® Core™2 Extreme processor X6800 and Intel® Core™2 Duo desktop
AI = processor E6000 and E4000 sequence
AJ = Quad-Core Intel® Xeon® processor 5300 series
Intel® Core™2 Extreme quad-core processor QX6000 sequence and Intel®
AK = Core™2 Quad processor Q6000 sequence
AL = Dual-Core Intel® Xeon® processor 7100 series
AM = Intel® Celeron® processor 400 sequence
AN = Intel® Pentium® dual-core processor
AO = Quad-Core Intel® Xeon® processor 3200 series
AP = Dual-Core Intel® Xeon® processor 3000 series
AQ = Intel® Pentium® dual-core desktop processor E2000 sequence
AR = Intel® Celeron® processor 500 series
AS = Intel® Xeon® processor 7200, 7300 series
AV = Intel® Core™2 Extreme processor QX9650 and Intel® Core™2 Quad processor
Q9000 series
AW = Intel® Core™ 2 Duo processor E8000 series
AX = Quad-Core Intel® Xeon® processor 5400 series
AY= Dual-Core Intel® Xeon® processor 5200 series
Intel® Core™2 Duo Processor and Intel® Core™2 Extreme Processor on 45-
AZ = nm Process
AAA = Quad-Core Intel® Xeon® processor 3300 series
AAB =
Dual-Core Intel® Xeon® E3110 Processor
AAC =
Intel® Celeron® dual-core processor E1000 series
AAD = Intel® Core™2 Extreme Processor QX9775Δ
AAE = Intel® Atom™ processor Z5xx series
The Specification Updates for the Pentium
other Intel products do not use this convention.
NO B1 B2 L2
AI1 X X X
AI2 X X X
AI3 X X X
AI4 X X X
AI5 X X X
AI6 X X X
AI7 X X X
10
M0 G0 Plan ERRATA
Writing the Local Vector Table (LVT) when an Interrupt is Pending May
X X No Fix
Cause an Unexpected Interrupt
LOCK# Asserted During a Special Cycle Shutdown Transaction May
X X No Fix
Unexpectedly De-assert
Address Reported by Machine-Check Architecture (MCA) on Single-bit
X X No Fix
L2 ECC Errors May be Incorrect
VERW/VERR/LSL/LAR Instructions May Unexpectedly Update the Last
X X No Fix
Exception Record (LER) MSR
DR3 Address Match on MOVD/MOVQ/MOVNTQ Memory Store Instruction
X X No Fix May Incorrectly Increment Performance Monitoring Count for Saturating
SIMD Instructions Retired (Event CFH)
X Fixed SYSRET May Incorrectly Clear RF (Resume Flag) in the RFLAGS Register
General Protection Fault (#GP) for Instructions Greater than 15 Bytes
X X No Fix
May be Preempted
Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence
Summary Tables of Changes
® ®
processor, Pentium
®
Intel Core™2 Extreme Processor X6800 and
Pro processor, and
Specification Update