Intel CORE 2 DUO E4000 - SPECIFICATION UPDATE 3-2008 Specification page 13

Summary Tables of Changes
NO B1 B2 L2
AI51 X X X
AI52 X X X
AI53 X X X
AI54 X X X
AI55 X X X
AI56 X X X
AI57 X X X
AI58 X X X
AI59 X X X
AI60 X X X
AI61 X X X
AI62 X X X
AI63 X X X
AI64 X X X
AI65 X X X
AI66 X X X
AI67 X X X
AI68 X X X
AI69 X X X
AI70 X X X
AI71 X X X
AI72 X X X
®
Intel Core™2 Extreme Processor X6800 and
®
Intel Core™2 Duo Desktop Processor E6000 and E4000 Sequence
Specification Update
M0 G0 Plan ERRATA
An Enabled Debug Breakpoint or Single Step Trap May Be Taken after
X X No Fix MOV SS/POP SS Instruction if it is Followed by an Instruction That
Signals a Floating Point Exception
Last Branch Records (LBR) Updates May be Incorrect after a Task
X X No Fix
Switch
X X No Fix IO_SMI Indication in SMRAM State Save Area May Be Set Incorrectly
X X No Fix INIT Does Not Clear Global Entries in the TLB
Using Memory Type Aliasing with Memory Types WB/WT May Lead to
X Fixed
Unpredictable Behavior
Update of Read/Write (R/W) or User/Supervisor (U/S) or Present (P)
X Fixed
Bits without TLB Shootdown May Cause Unexpected Processor Behavior
X Fixed BTS Message May Be Lost When the STPCLK# Signal is Active
CMPSB, LODSB, or SCASB in 64-bit Mode with Count Greater or Equal
X X No Fix
to 2
REP MOVS/STOS Executing with Fast Strings Enabled and Crossing Page
X X No Fix Boundaries with Inconsistent Memory Types may use an Incorrect Data
Size or Lead to Memory-Ordering Violations.
X X No Fix MOV To/From Debug Registers Causes Debug Exception
Debug Register May Contain Incorrect Information on a MOVSS or
X Fixed
POPSS Instruction Followed by SYSRET
EFLAGS Discrepancy on a Page Fault After a Multiprocessor TLB
X X No Fix
Shootdown
LBR, BTS, BTM May Report a Wrong Address when an
X X No Fix
Exception/Interrupt Occurs in 64-bit Mode
Returning to Real Mode from SMM with EFLAGS.VM Set May Result in
X X No Fix
Unpredictable System Behavior
A Thermal Interrupt is Not Generated when the Current Temperature is
X X No Fix
Invalid
VMLAUNCH/VMRESUME May Not Fail when VMCS is Programmed to
X Fixed
Cause VM Exit to Return to a Different Mode
IRET under Certain Conditions May Cause an Unexpected Alignment
X X No Fix
Check Exception
X X No Fix Performance Monitoring Event FP_ASSIST May Not be Accurate
CPL-Qualified BTS May Report Incorrect Branch-From Instruction
X Fixed
Address
X Fixed PEBS Does Not Always Differentiate Between CPL-Qualified Events
X X No Fix PMI May Be Delayed to Next PEBS Event
PEBS Buffer Overflow Status Will Not be Indicated Unless
X Fixed
IA32_DEBUGCTL[12] is Set
48 May Terminate Early
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