Intel CORE 2 DUO E4000 - SPECIFICATION UPDATE 3-2008 Specification page 52

first load may get the data from external memory or L2 written by another
core, while the second load will get the data straight from the WT Store.
Implication: Software that uses WB to WT memory aliasing may violate proper store
ordering.
Workaround: Do not use WB to WT aliasing.
For the steppings affected, see the Summary Tables of Changes.
Status:
AI82. A MOV Instruction from CR8 Register with 16 Bit Operand Size
Will Leave Bits 63:16 of the Destination Register Unmodified
Moves to/from control registers are supposed to ignore REW.W and the 66H
Problem:
(operand size) prefix. In systems supporting Intel
when the processor is operating in VMX non-root operation and "use TPR
shadow" VM-execution control is set to 1, a MOV instruction from CR8 with a
16 bit operand size (REX.W =0 and 66H prefix) will only store 16 bits and
leave bits 63:16 at the destination register unmodified, instead of
storing zeros in them.
Implication: Intel has not observed this erratum with any commercially available software.
Workaround: None identified.
For the steppings affected, see the Summary Tables of Changes.
Status:
AI83. Non-Temporal Data Store May be Observed in Wrong Program Order
When non-temporal data is accessed by multiple read operations in one
Problem:
thread while another thread performs a cacheable write operation to the
same address, the data stored may be observed in wrong program order (i.e.
later load operations may read older data).
Implication: Software that uses non-temporal data without proper serialization before
accessing the non-temporal data may observe data in wrong program order.
Workaround: Software that conforms to the Intel
Developer's Manual, Volume 3A, section "Buffering of Write Combining
Memory Locations" will operate correctly.
For the steppings affected, see the Summary Tables of Changes.
Status:
AI84. Performance Monitor SSE Retired Instructions May Return Incorrect
Values
Performance Monitoring counter SIMD_INST_RETIRED (Event: C7H) is used
Problem:
to track retired SSE instructions. Due to this erratum, the processor may
inaccurately also count certain other types of instructions resulting in higher
than expected values.
52
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64 and IA-32 Architectures Software
Intel
Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence
®
Virtualization Technology,
®
Core™2 Extreme Processor X6800 and
Specification Update
Errata