Intel CORE 2 DUO E4000 - SPECIFICATION UPDATE 3-2008 Specification page 43

Errata
For the steppings affected, see the Summary Tables of Changes.
Status:
AI56. Update of Read/Write (R/W) or User/Supervisor (U/S) or Present
(P) Bits without TLB Shootdown May Cause Unexpected Processor
Behavior
Updating a page table entry by changing R/W, U/S or P bits without TLB
Problem:
shootdown (as defined by the 4 step procedure in "Propagation of Page Table
and Page Directory Entry Changes to Multiple Processors" In volume 3A of the
IA-32 Intel
complex sequence of internal processor micro-architectural events, may lead
to unexpected processor behavior.
Implication: This erratum may lead to livelock, shutdown or other unexpected processor
behavior. Intel has not observed this erratum with any commercially available
system.
Workaround: None Identified.
For the steppings affected, see the Summary Tables of Changes.
Status:
AI57. BTS Message May Be Lost When the STPCLK# Signal is Active.
STPCLK# is asserted to enable the processor to enter a low-power state.
Problem:
Under some circumstances, when STPCLK# becomes active, the BTS (Branch
Trace Store) message may be either lost and not written or written with
corrupted branch address to the Debug Store area
Implication: BTS messages may be lost or be corrupted in the presence of STPCLK#
assertions.
Workaround: None Identified.
For the steppings affected, see the Summary Tables of Changes.
Status:
AI58. CMPSB, LODSB, or SCASB in 64-bit Mode with Count Greater or Equal
48
to 2 May Terminate Early
In 64-bit Mode CMPSB, LODSB, or SCASB executed with a repeat prefix and
Problem:
count greater than or equal to 2
may result in one of the following.
• The last iteration not being executed
• Signaling of a canonical limit fault (#GP) on the last iteration
Implication: While in 64-bit mode, with count greater or equal to 2
operations CMPSB, LODSB or SCASB may terminate without completing the
last iteration. Intel has not observed this erratum with any commercially
available software.
®
Intel Core™2 Extreme Processor X6800 and
®
Intel Core™2 Duo Desktop Processor E6000 and E4000 Sequence
Specification Update
®
Architecture Software Developer's Manual), in conjunction with a
48
may terminate early. Early termination
48
, repeat string
43