Intel CORE 2 DUO E4000 - SPECIFICATION UPDATE 3-2008 Specification page 44

Workaround: Do not use repeated string operations with RCX greater than or equal to 2
For the steppings affected, see the Summary Tables of Changes.
Status:
AI59. REP MOVS/STOS Executing with Fast Strings Enabled and Crossing
Page Boundaries with Inconsistent Memory Types may use an
Incorrect Data Size or Lead to Memory-Ordering Violations.
Under certain conditions as described in the Software Developers Manual
Problem:
section "Out-of-Order Stores For String Operations in Pentium 4, Intel Xeon,
and P6 Family Processors" the processor performs REP MOVS or REP STOS as
fast strings. Due to this erratum fast string REP MOVS/REP STOS instructions
that cross page boundaries from WB/WC memory types to UC/WP/WT
memory types, may start using an incorrect data size or may observe
memory ordering violations.
Implication: Upon crossing the page boundary the following may occur, dependent on the
new page memory type:
• UC the data size of each write will now always be 8 bytes, as opposed to the
original data size.
• WP the data size of each write will now always be 8 bytes, as opposed to the
original data size and there may be a memory ordering violation.
• WT there may be a memory ordering violation.
Workaround: Software should avoid crossing page boundaries from WB or WC memory
type to UC, WP or WT memory type within a single REP MOVS or REP STOS
instruction that will execute with fast strings enabled.
For the steppings affected, see the Summary Tables of Changes.
Status:
AI60. MOV To/From Debug Registers Causes Debug Exception
When in V86 mode, if a MOV instruction is executed to/from on debug
Problem:
register, a general-protection exception (#GP) should be generated.
However, in the case when the general detect enable flag (GD) bit is set, the
observed behavior is that a debug exception (#DB) is generated instead.
Implication: With debug-register protection enabled (i.e., the GD bit set), when
attempting to execute a MOV on debug registers in V86 mode, a debug
exception will be generated instead of the expected general-protection fault.
Workaround: In general, operating systems do not set the GD bit when they are in V86
mode. The GD bit is generally set and used by debuggers. The debug
exception handler should check that the exception did not occur in V86 mode
before continuing. If the exception did occur in V86 mode, the exception may
be directed to the general-protection exception handler.
For the steppings affected, see the Summary Tables of Changes.
Status:
AI61. Debug Register May Contain Incorrect Information on a MOVSS or
POPSS Instruction Followed by SYSRET
44 Intel
Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence
®
Core™2 Extreme Processor X6800 and
Specification Update
Errata
48
.