Intel CORE 2 DUO E4000 - SPECIFICATION UPDATE 3-2008 Specification page 61

Errata
Workaround: Software should not attempt to set reserved bits of IA32_MTRR_PHYSMASKn
MSRs.
For the steppings affected, see the Summary Tables of Changes.
Status:
AI107. PMI While LBR Freeze Enabled May Result in Old/Out-of-date LBR
Information
When Precise Event-Based Sampling (PEBS) is configured with Performance
Problem:
Monitoring Interrupt (PMI) on PEBS buffer overflow enabled and Last Branch
Record (LBR) Freeze on PMI enabled by setting FREEZE_LBRS_ON_PMI flag
(bit 11) to 1 in IA32_DEBUGCTL (MSR 1D9H), the LBR stack is frozen upon
the occurrence of a hardware PMI request. Due to this erratum, the LBR
freeze may occur too soon (i.e. before the hardware PMI request).
Implication: Following a PMI occurrence, the PMI handler may observe old/out-of-date
LBR information that does not describe the last few branches before the PEBS
sample that triggered the PMI.
Workaround: None identified.
For the steppings affected, see the Summary Tables of Changes.
Status:
AI108. VMCALL failure due to corrupt MSEG location may cause VM Exit to
load the machine state incorrectly
In systems supporting Intel® Virtualization Technology, if a VMCALL failure
Problem:
occurs due to a corrupt Monitor Segment (MSEG), subsequent VM Exits may
load machine state incorrectly.
Implication: Occurrence of this erratum may result in a VMX abort.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
For the steppings affected, see the Summary Tables of Changes.
Status:
AI109. Overlap of an Intel® VT APIC Access Page in a Guest with the DS
Save Area May Lead to Unpredictable Behavior
Logging of a branch record or a PEBS (precise-event-based-sampling) record
Problem:
to the DS (debug store) save area that overlaps with the APIC access page
may lead to unpredictable behavior.
Implication: Guest software configured to log branch records or PEBS records
cannot specify the DS (debug store) save area within the APIC-access page.
Under any expected usage model this type of overlap is not expected to exist.
One should be aware of the fact that the specified DS address is of linear
form while the APIC access page is of a physical form. Any solution that
wishes to avoid this condition will need to comprehend the linear-to-physical
translation of the DS related address pointers with respect to the mapping of
®
Intel Core™2 Extreme Processor X6800 and
®
Intel Core™2 Duo Desktop Processor E6000 and E4000 Sequence
Specification Update
61