Intel CORE 2 DUO E4000 - SPECIFICATION UPDATE 3-2008 Specification page 12

NO B1 B2 L2
AI30 X X
AI31 X X X
AI32 X X X
AI33 X X X
AI34 X X X
AI35 X X X
AI36 X X X
AI37 X X
AI38 X X X
AI39 X X X
AI40 X X X
AI41 X X X
AI42 X X X
AI43 X X X
AI44 X X X
AI45 X X X
AI46 X X X
AI47 X X
AI48 X X X
AI49 X X X
AI50 X X X
12
M0 G0 Plan ERRATA
(E)CX May Get Incorrectly Updated When Performing Fast String REP
Fixed
MOVS or Fast String REP STOS With Large Data Structures
Performance Monitoring Events for Retired Loads (CBH) and Instructions
X Fixed
Retired (C0H) May Not Be Accurate
Upper 32 bits of 'From' Address Reported through BTMs or BTSs May be
X X No Fix
Incorrect
Unsynchronized Cross-Modifying Code Operations Can Cause
Fixed
Unexpected Instruction Execution Results
MSRs Actual Frequency Clock Count (IA32_APERF) or Maximum
X X No Fix Frequency Clock Count (IA32_MPERF) May Contain Incorrect Data after
a Machine Check Exception (MCE)
Incorrect Address Computed For Last Byte of FXSAVE/FXRSTOR Image
X X No Fix
Leads to Partial Memory Update
X X No Fix Split Locked Stores May not Trigger the Monitoring Hardware
REP CMPS/SCAS Operations May Terminate Early in 64-bit Mode when
Fixed
RCX >= 0X100000000
FXSAVE/FXRSTOR Instructions which Store to the End of the Segment
X Fixed and Cause a Wrap to a Misaligned Base Address (Alignment <= 0x10h)
May Cause FPU Instruction or Operand Pointer Corruption
Cache Data Access Request from One Core Hitting a Modified Line in the
X Fixed L1 Data Cache of the Other Core May Cause Unpredictable System
Behavior
PREFETCHh Instruction Execution under Some Conditions May Lead to
X Fixed
Processor Livelock
PREFETCHh Instructions May Not be Executed when Alignment Check
X Fixed
(AC) is Enabled
Upper 32 Bits of the FPU Data (Operand) Pointer in the FXSAVE Memory
X Fixed
Image May Be Unexpectedly All 1's after FXSAVE
Concurrent Multi-processor Writes to Non-dirty Page May Result in
Fixed
Unpredictable Behavior
Performance Monitor IDLE_DURING_DIV (18h) Count May Not be
X Fixed
Accurate
X X No Fix Values for LBR/BTS/BTM will be Incorrect after an Exit from SMM
X X No Fix Shutdown Condition May Disable Non-Bootstrap Processors
SYSCALL Immediately after Changing EFLAGS.TF May Not Behave
Fixed
According to the New EFLAGS.TF
Code Segment Limit/Canonical Faults on RSM May be Serviced before
X X No Fix
Higher Priority Interrupts/Exceptions
VM Bit is Cleared on Second Fault Handled by Task Switch from Virtual-
X X No Fix
8086 (VM86)
X Fixed IA32_FMASK is Reset during an INIT
Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence
Summary Tables of Changes
®
Intel Core™2 Extreme Processor X6800 and
Specification Update