Intel CORE 2 DUO E4000 - SPECIFICATION UPDATE 3-2008 Specification page 63

Errata
Performance Monitor Event FP_MMX_TRANS_TO_MMX (Event CCH, Umask
Problem:
01H) counts transitions from x87 Floating Point (FP) to MMX™ instructions.
Due to this erratum, if only a small number of MMX instructions (including
EMMS) are executed immediately after the last FP instruction, a FP to MMX
transition may not be counted.
Implication: The count value for Performance Monitoring Event FP_MMX_TRANS_TO_MMX
may be lower than expected. The degree of undercounting is dependent on
the occurrences of the erratum condition while the counter is active. Intel has
not observed this erratum with any commercially available software.
Workaround: None identified.
For the steppings affected, see the Summary Tables of Changes.
Status:
AI113. When One Core Executes SEXIT the Other Core's Last Branch
Recording May be Incorrect
In processors supporting Intel® Trusted Execution Technology when one core
Problem:
is executing SEXIT and the other core is executing a control-transfer
instruction, the FROM_IP field contained in the last branch information may
be incorrect for the following:
• LBR (Last Branch Record) MSRs
• BTM (Branch Traces Messages) on the bus
• BTS (Branch Trace Store) records written by the debug store mechanism
Implication: Due to this erratum, last branch information may be incorrect after one core
executes SEXIT. Intel has not observed this erratum with any commercially
available software.
Workaround: None identified.
For the steppings affected, see the Summary Tables of Changes.
Status:
AI114. A GETSEC[ENTERACCS] Instruction Executed Immediately after
GETSEC[WAKEUP] Instruction May Result in a Processor Hang
In dual core processor systems supporting Intel® Trusted Execution
Problem:
Technology, a processor hang or unpredictable system behavior may occur if
the ILP (Initiating Logical Processor) executes GETSEC[WAKEUP] and then
executes GETSEC[ENTERACCS] without making sure that the RLP
(Responding Logical Processor) has woken up in between these two
instructions.
Implication: This may cause the processor to hang or execute code down an unintended
path.
®
Intel Core™2 Extreme Processor X6800 and
®
Intel Core™2 Duo Desktop Processor E6000 and E4000 Sequence
Specification Update
63