Intel CORE 2 DUO E4000 - SPECIFICATION UPDATE 3-2008 Specification page 55

Errata
Implication: When this erratum occurs, a non-accessed page which is present in memory
and follows a page that contains the code segment limit may be tagged as
accessed.
Workaround: Erratum can be avoided by placing a guard page (non-present or non-
executable page) as the last page of the segment or after the page that
includes the code segment limit.
For the steppings affected, see the Summary Tables of Changes.
Status:
AI91. Update of Attribute Bits on Page Directories without Immediate TLB
Shootdown May Cause Unexpected Processor Behavior
Updating a page directory entry (or page map level 4 table entry or page
Problem:
directory pointer table entry in IA-32e mode) by changing read/Write (R/W)
or User/Supervisor (U/S) or Present (P) bits without immediate TLB
shootdown (as described by the 4 step procedure in "Propagation of Page
Table and Page Directory Entry Changes to Multiple Processors" In volume 3A
of the Intel® 64 and IA-32 Architecture Software Developer's Manual), in
conjunction with a complex sequence of internal processor micro-architectural
events, may lead to unexpected processor behavior.
Implication: This erratum may lead to livelock, shutdown or other unexpected processor
behavior. Intel has not observed this erratum with any commercially
available software.
Workaround: None Identified.
For the steppings affected, see the Summary Tables of Changes.
Status:
AI92. Invalid Instructions May Lead to Unexpected Behavior
Implication: Invalid instructions due to undefined opcodes or instructions exceeding the
maximum instruction length (due to redundant prefixes placed before the
instruction) may lead, under complex circumstances, to unexpected behavior.
Implication: The processor may behave unexpectedly due to invalid instructions. Intel has
not observed this erratum with any commercially available software.
Workaround: None identified.
For the steppings affected, see the Summary Tables of Changes.
Status:
AI93. EFLAGS, CR0, CR4 and the EXF4 Signal May be Incorrect after
Shutdown
When the processor is going into shutdown due to an RSM inconsistency
Problem:
failure, EFLAGS, CR0 and CR4 may be incorrect. In addition the EXF4 signal
®
Intel Core™2 Extreme Processor X6800 and
®
Intel Core™2 Duo Desktop Processor E6000 and E4000 Sequence
Specification Update
55