Intel CORE 2 DUO E4000 - SPECIFICATION UPDATE 3-2008 Specification page 11

Summary Tables of Changes
NO B1 B2 L2
AI8 X X X
AI9 X X X
AI10 X X X
AI11 X X X
AI12 X X X
AI13 X X X
AI14 X X X
AI15 X X X
AI16 X X X
AI17 X X X
AI18 X X X
AI19 X X X
AI20 X X X
AI21 X X X
AI22 X X X
AI23 X X X
AI24 X X X
AI25 X X X
AI26 X X X
AI27 X X X
AI28 X X X
AI29 X X X
®
Intel Core™2 Extreme Processor X6800 and
®
Intel Core™2 Duo Desktop Processor E6000 and E4000 Sequence
Specification Update
M0 G0 Plan ERRATA
Pending x87 FPU Exceptions (#MF) Following STI May Be Serviced
X X No Fix
Before Higher Priority Interrupts
X X No Fix The Processor May Report a #TS Instead of a #GP Fault
Single Step Interrupts with Floating Point Exception Pending May Be
X X No Fix
Mishandled
A Write to an APIC Register Sometimes May Appear to Have Not
X X No Fix
Occurred
Programming the Digital Thermal Sensor (DTS) Threshold May Cause
X X No Fix
Unexpected Thermal Interrupts
Count Value for Performance-Monitoring Counter PMH_PAGE_WALK May
X X No Fix
be Incorrect
X X No Fix LER MSRs May be Incorrectly Updated
Performance Monitoring Events for Retired Instructions (C0H) May Not
X X No Fix
Be Accurate
Performance Monitoring Event For Number Of Reference Cycles When
X X No Fix The Processor Is Not Halted (3CH) Does Not Count According To The
Specification
Using 2M/4M Pages When A20M# Is Asserted May Result in Incorrect
X X No Fix
Address Translations
Writing Shared Unaligned Data that Crosses a Cache Line without
X X No Fix
Proper Semaphores or Barriers May Expose a Memory Ordering Issue
X X No Fix Code Segment Limit Violation May Occur on 4 Gigabyte Limit Check
X Fixed FP Inexact-Result Exception Flag May Not Be Set
Global Pages in the Data Translation Look-Aside Buffer (DTLB) May Not
X Fixed Be Flushed by RSM instruction before Restoring the Architectural State
from SMRAM
Sequential Code Fetch to Non-canonical Address May have Non-
X Fixed
deterministic Results
VMCALL to Activate Dual-monitor Treatment of SMIs and SMM Ignores
X Fixed
Reserved Bit settings in VM-exit Control Field
X X No Fix The PECI Controller Resets to the Idle State
Some Bus Performance Monitoring Events May Not Count Local Events
X X No Fix
under Certain Conditions
Premature Execution of a Load Operation Prior to Exception Handler
X X No Fix
Invocation
General Protection (#GP) Fault May Not Be Signaled on Data Segment
X X No Fix
Limit Violation above 4-G Limit
X X No Fix EIP May be Incorrect after Shutdown in IA-32e Mode
#GP Fault is Not Generated on Writing IA32_MISC_ENABLE [34] When
X X No Fix
Execute Disable Bit is Not Supported
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