Intel CORE 2 DUO E4000 - SPECIFICATION UPDATE 3-2008 Specification page 14

NO B1 B2 L2
AI73 X X X
AI74 X X X
AI75 X X X
AI76 X X X
AI77 X X X
AI78 X X X
AI79 X X X
AI80 X X X
AI81 X X X
AI82 X X X
AI83 X X X
AI84 X X X
AI85 X X X
AI86 X X
AI87 X X X
AI88 X X X
AI89 X X X
AI90 X X X
AI91 X X X
AI92 X X X
AI93 X X X
AI94 X X X
AI95 X X X
14
M0 G0 Plan ERRATA
X X No Fix The BS Flag in DR6 May be Set for Non-Single-Step #DB Exception
X X No Fix An Asynchronous MCE During a Far Transfer May Corrupt ESP
In Single-Stepping on Branches Mode, the BS Bit in the Pending-Debug-
X Fixed Exceptions Field of the Guest State Area will be Incorrectly Set by VM-
Exit on a MOV to CR8 Instruction
X X No Fix B0-B3 Bits in DR6 May Not be Properly Cleared After Code Breakpoint
BTM/BTS Branch-From Instruction Address May be Incorrect for
X X No Fix
Software Interrupts
Last Branch Records (LBR) Updates May be Incorrect After a Task
X X No Fix
Switch
REP Store Instructions in a Specific Situation may cause the Processor
X Fixed
to Hang
X X No Fix Performance Monitoring Events for L1 and L2 Miss May Not be Accurate
Store to WT Memory Data May be Seen in Wrong Order by Two
X X No Fix
Subsequent Loads
A MOV Instruction from CR8 Register with 16 Bit Operand Size
X X No Fix
Will Leave Bits 63:16 of the Destination Register Unmodified
X X No Fix Non-Temporal Data Store May be Observed in Wrong Program Order
Performance Monitor SSE Retired Instructions May Return Incorrect
X X No Fix
Values
Fault on ENTER Instruction May Result in Unexpected Values on Stack
X X No Fix
Frame
CPUID Reports Architectural Performance Monitoring Version 2 is
Fixed
Supported, When Only Version 1 Capabilities are Available
Unaligned Accesses to Paging Structures May Cause the Processor to
X X No Fix
Hang
Microcode Updates Performed During VMX Non-root Operation Could
X X No Fix
Result in Unexpected Behavior
INVLPG Operation for Large (2M/4M) Pages May be Incomplete under
X X No Fix
Certain Conditions
Page Access Bit May be Set Prior to Signaling a Code Segment Limit
X X No Fix
Fault
Update of Attribute Bits on Page Directories without Immediate TLB
X Fixed
Shootdown May Cause Unexpected Processor Behavior
X Fixed Invalid Instructions May Lead to Unexpected Behavior
EFLAGS, CR0, CR4 and the EXF4 Signal May be Incorrect after
X X No Fix
Shutdown
Performance Monitoring Counter MACRO_INSTS.DECODED May Not
X Fixed
Count Some Decoded Instructions
The Stack Size May be Incorrect as a Result of VIP/VIF Check on
X Fixed
SYSEXIT and SYSRET
Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence
Summary Tables of Changes
®
Intel Core™2 Extreme Processor X6800 and
Specification Update