Intel CORE 2 DUO E4000 - SPECIFICATION UPDATE 3-2008 Specification page 47

Errata
For the steppings affected, see the Summary Tables of Changes.
Status:
AI66. VMLAUNCH/VMRESUME May Not Fail when VMCS is Programmed to
Cause VM Exit to Return to a Different Mode
VMLAUNCH/VMRESUME instructions may not fail if the value of the "host
Problem:
address-space size" VM-exit control differs from the setting of
IA32_EFER.LMA.
Implication: Programming the VMCS to allow the monitor to be in different modes prior to
VMLAUNCH/VMRESUME and after VM-exit may result in undefined behavior
Workaround: Software should ensure that "host address-space size" VM-exit control has
the same value as IA32_EFER.LMA at the time of VMLAUNCH/VMRESUME.
For the steppings affected, see the Summary Tables of Changes.
Status:
AI67. IRET under Certain Conditions May Cause an Unexpected Alignment
Check Exception
In IA-32e mode, it is possible to get an Alignment Check Exception (#AC) on
Problem:
the IRET instruction even though alignment checks were disabled at the start
of the IRET. This can only occur if the IRET instruction is returning from CPL3
code to CPL3 code. IRETs from CPL0/1/2 are not affected. This erratum can
occur if the EFLAGS value on the stack has the AC flag set, and the interrupt
handler's stack is misaligned. In IA-32e mode, RSP is aligned to a 16-byte
boundary before pushing the stack frame.
Implication: In IA-32e mode, under the conditions given above, an IRET can get a #AC
even if alignment checks are disabled at the start of the IRET. This erratum
can only be observed with a software generated stack frame.
Workaround: Workaround: Software should not generate misaligned stack frames for use
with IRET.
For the steppings affected, see the Summary Tables of Changes.
Status:
AI68. Performance Monitoring Event FP_ASSIST May Not be Accurate
Performance monitoring event FP_ASSIST (11H) may be inaccurate as assist
Problem:
events will be counted twice per actual assist in the following specific cases:
• FADD and FMUL instructions with a NaN(Not a Number) operand and a memory
operand
• FDIV instruction with zero operand value in memory
In addition, an assist event may be counted when DAZ (Denormals-Are-Zeros) and
FTZ (Flush-To-Zero) flags are turned on even though no actual assist occurs.
®
Intel Core™2 Extreme Processor X6800 and
®
Intel Core™2 Duo Desktop Processor E6000 and E4000 Sequence
Specification Update
47