Intel CORE 2 DUO E4000 - SPECIFICATION UPDATE 3-2008 Specification page 42

The IO_SMI bit in SMRAM's location 7FA4H is set to "1" by the CPU to
Problem:
indicate a System Management Interrupt (SMI) occurred as the result of
executing an instruction that reads from an I/O port. Due to this erratum, the
IO_SMI bit may be incorrectly set by
• A non-I/O instruction.
• SMI is pending while a lower priority event interrupts
• A REP I/O read
• An I/O read that redirects to MWAIT
• In systems supporting Intel
IO operation that causes a VM Exit
Implication: SMM handlers may get false IO_SMI indication.
Workaround: The SMM handler has to evaluate the saved context to determine if the SMI
was triggered by an instruction that read from an I/O port. The SMM handler
must not restart an I/O instruction if the platform has not been configured to
generate a synchronous SMI for the recorded I/O port address.
For the steppings affected, see the Summary Tables of Changes.
Status:
AI54. INIT Does Not Clear Global Entries in the TLB
INIT may not flush a TLB entry when:
Problem:
• The processor is in protected mode with paging enabled and the page global
enable flag is set (PGE bit of CR4 register)
• G bit for the page table entry is set
• TLB entry is present in TLB when INIT occurs
Implication: Software may encounter unexpected page fault or incorrect address
translation due to a TLB entry erroneously left in TLB after INIT.
Workaround: Write to CR3, CR4 (setting bits PSE, PGE or PAE) or CR0 (setting bits PG or
PE) registers before writing to memory early in BIOS code to clear all the
global entries from TLB.
For the steppings affected, see the Summary Tables of Changes.
Status:
AI55. Using Memory Type Aliasing with Memory Types WB/WT May Lead to
Unpredictable Behavior
Memory type aliasing occurs when a single physical page is mapped to two or
Problem:
more different linear addresses, each with different memory type. Memory
type aliasing with the memory types WB and WT may cause the processor to
perform incorrect operations leading to unpredictable behavior.
Implication: Software that uses aliasing of WB and WT memory types may observe
unpredictable behavior.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
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®
Virtualization Technology a fault in the middle of an
Intel
Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence
®
Core™2 Extreme Processor X6800 and
Specification Update
Errata