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2.7.3
Processor DC Specifications
The processor DC specifications in this section are defined at the processor core (pads)
unless otherwise stated. All specifications apply to all frequencies and cache sizes
unless otherwise stated.
Table 10.
GTL+ Signal Group DC Specifications
Symbol
V
IL
V
IH
V
OH
I
OL
I
LI
I
LO
R
ON
NOTES:
1.
Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2.
V
IL
low value.
3.
V
IH
high value.
4.
V
IH
5.
The V
6.
Leakage to V
7.
Leakage to V
Table 11.
Open Drain and TAP Output Signal Group DC Specifications
Symbol
V
OL
I
OL
I
LO
NOTES:
1.
Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2.
Measured at V
3.
For Vin between 0 and V
24
Parameter
Input Low Voltage
Input High Voltage
GTLREF + 0.10
Output High Voltage
Output Low Current
Input Leakage
Current
Output Leakage
Current
Buffer On Resistance
is defined as the voltage range at a receiving agent that will be interpreted as a logical
is defined as the voltage range at a receiving agent that will be interpreted as a logical
and V
may experience excursions above V
OH
referred to in these specifications is the instantaneous V
TT
with land held at V
SS
with land held at 300 mV.
TT
Parameter
Output Low Voltage
Output Low Current
Output Leakage Current
* 0.2 V.
TT
.
OH
Min
-0.10
GTLREF – 0.10
V
TT
V
– 0.10
TT
V
TT_MAX
N/A
[(R
) + (2 * R
TT_MIN
N/A
± 100
N/A
± 100
7.49
.
TT
.
TT
Min
0
16
N/A
Electrical Specifications
Max
Unit
Notes
V
+ 0.10
V
V
V
TT
/
A
)]
ON_MIN
µA
µA
9.16
.
TT
Max
Unit
Notes
0.20
V
50
mA
± 200
µA
Datasheet
1
2, 5
3, 4, 5
4, 5
-
6
7
1
-
2
3
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