Fsb Signal Groups - Intel E6300 - Core 2 Duo Dual-Core Processor Datasheet

2.7.1

FSB Signal Groups

The front side bus signals have been combined into groups by buffer type. GTL+ input
signals have differential input buffers, which use GTLREF[1:0] as a reference level. In
this document, the term "GTL+ Input" refers to the GTL+ input group as well as the
GTL+ I/O group when receiving. Similarly, "GTL+ Output" refers to the GTL+ output
group as well as the GTL+ I/O group when driving.
With the implementation of a source synchronous data bus comes the need to specify
two sets of timing parameters. One set is for common clock signals which are
dependent on the rising edge of BCLK0 (ADS#, HIT#, HITM#, and so forth) and the
second set is for the source synchronous signals that are relative to their respective
strobe lines (data and address) as well as the rising edge of BCLK0. Asychronous
signals are still present (A20M#, IGNNE#, and so forth) and can become active at any
time during the clock cycle.
synchronous, and asynchronous.
Table 7.

FSB Signal Groups

Signal Group
GTL+ Common
Clock Input
GTL+ Common
Clock I/O
GTL+ Source
Synchronous I/O
GTL+ Strobes
CMOS
Open Drain Output
Open Drain Input/
Output
FSB Clock
Power/Other
NOTES:
1. See
2. In processor systems where no debug port is implemented on the system board, these
signals are used to support a debug port interposer. In systems with the debug port
implemented on the system board, these signals are no connects.
3. The value of these signals during the active-to-inactive edge of RESET# defines the
processor configuration options. See
4. PROCHOT# signal type is open drain output and CMOS input.
22
Table 7
Type
Synchronous to
BCLK[1:0]
Synchronous to
BCLK[1:0]
Synchronous to
assoc. strobe
Synchronous to
BCLK[1:0]
Clock
Section 4.2 for signal descriptions.
identifies which signals are common clock, source
Signals
BPRI#, DEFER#, RESET#, RS[2:0]#, TRDY#
ADS#, BNR#, BPM[5:0]#, BR0#
HITM#, LOCK#
Signals
3
REQ[4:0]#, A[16:3]#
3
A[35:17]#
D[15:0]#, DBI0#
D[31:16]#, DBI1#
D[47:32]#, DBI2#
D[63:48]#, DBI3#
ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]#
A20M#, DPRSTP#. DPSLP#, IGNNE#, INIT#, LINT0/INTR,
3
LINT1/NMI, SMI# , STPCLK#, PWRGOOD, SLP#, TCK, TDI,
TMS, TRST#, BSEL[2:0], VID[7:0], PSI#
FERR#/PBE#, IERR#, THERMTRIP#, TDO
4
PROCHOT#
2
BCLK[1:0], ITP_CLK[1:0]
VCC, VTT, VCCA, VCCIOPLL, VCCPLL, VSS, VSSA,
GTLREF[1:0], COMP[8,3:0], RESERVED, TESTHI[12,10:0],
VCC_SENSE, VCC_MB_REGULATION, VSS_SENSE,
VSS_MB_REGULATION, DBR#
VTT_OUT_RIGHT, VTT_SEL, FCx, PECI, MSID[1:0]
Section 6.1 for details.
Electrical Specifications
1
3
, DBSY#, DRDY#, HIT#,
Associated Strobe
ADSTB0#
ADSTB1#
DSTBP0#, DSTBN0#
DSTBP1#, DSTBN1#
DSTBP2#, DSTBN2#
DSTBP3#, DSTBN3#
2
, VTT_OUT_LEFT,
Datasheet