Input Device Hysteresis; Peci Dc Electrical Limits - Intel E5410 - Cpu Xeon Quad Core 2.33Ghz Fsb1333Mhz 12M Lga771 Tray Datasheet
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Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications
Table 2-10. PECI DC Electrical Limits
Symbol
V
hysteresis
I
source
I
I
C
V
Note:
1.
V
supplies the PECI interface. PECI behavior does not affect V
TT
2.
The leakage specification applies to powered devices on the PECI bus.
3.
One node is counted for each client and one node for the system host. Extended trace lengths might appear
as additional nodes.
2.10.2
Input Device Hysteresis
The input buffers in both client and host models must use a Schmitt-triggered input
design for improved noise immunity. Use
Figure 2-1.
Input Device Hysteresis
V
TT
Maximum V
Minimum V
Maximum V
Minimum V
PECI Ground
Definition and Conditions
V
Input Voltage Range
in
Hysteresis
Negative-edge threshold
V
n
voltage
Positive-edge threshold
V
p
voltage
High level output source
(V
= 0.75 * V
OH
Low level output sink
I
sink
(V
= 0.25 * V
OL
High impedance state leakage
to V
leak+
(V
leak
High impedance leakage to
GND
leak-
(V
leak
Bus capacitance per node
bus
Signal noise immunity above
noise
300 MHz
PECI High Range
P
P
N
PECI Low Range
N
Min
-0.150
0.1 * V
TT
0.275 * V
TT
0.550 * V
TT
-6.0
)
TT
0.5
)
TT
N/A
TT
= V
)
OL
N/A
= V
)
OH
N/A
0.1 * V
TT
min/max specifications.
TT
Figure 2-1
as a guide for input buffer design.
Max
Units
Notes
V
V
TT
N/A
V
0.500 * V
V
TT
0.725 * V
V
TT
N/A
mA
1.0
mA
50
µA
10
µA
10
pF
N/A
V
p-p
Minimum
Valid Input
Hysteresis
Signal Range
1
2
2
3
25
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