Intel E5405 - Cpu Xeon Quad Core 2.00Ghz Fsb1333Mhz 12M Lga771 Tray Specification page 37

AX66. LBR, BTS, BTM May Report a Wrong Address when an Exception/
Interrupt Occurs in 64-bit Mode
Problem: An exception/interrupt event should be transparent to the LBR (Last Branch Record),
BTS (Branch Trace Store) and BTM (Branch Trace Message) mechanisms. However,
during a specific boundary condition where the exception/interrupt occurs right after
the execution of an instruction at the lower canonical boundary (0x00007FFFFFFFFFFF)
in 64-bit mode, the LBR return registers will save a wrong return address with bits 63
to 48 incorrectly sign extended to all 1's. Subsequent BTS and BTM operations which
report the LBR will also be incorrect.
Implication: LBR, BTS and BTM may report incorrect information in the event of an exception/
interrupt.
Workaround: None Identified
Status: For the steppings affected, see the
AX67. The XRSTOR Instruction May Fail to Cause a General-Protection
Exception
Problem: The XFEATURE_ENABLED_MASK register (XCR0) bits [63:9] are reserved and must be
0; consequently, the XRSTOR instruction should cause a general-protection exception if
any of the corresponding bits in the XSTATE_BV field in the header of the XSAVE/
XRSTOR area is set to 1. Due to this erratum, a logical processor may fail to cause such
an exception if one or more of these reserved bits are set to 1.
Implication: Software may not operate correctly if it relies on the XRSTOR instruction to cause a
general-protection exception when any of the bits [63:9] in the XSTATE_BV field in the
header of the XSAVE/XRSTOR area is set to 1.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the
AX68. The XSAVE Instruction May Erroneously Modify Reserved Bits in the
XSTATE_BV Field
Problem: Bits 63:2 of the HEADER.XSTATE_BV are reserved and must be 0. Due to this erratum,
the XSAVE instruction may erroneously modify one or more of these bits.
Implication: If one of bits 63:2 of the XSTATE_BV field in the header of the XSAVE/XRSTOR area had
been 1 and was then cleared by the XSAVE instruction, a subsequent execution of
XRSTOR may not generate the #GP (general-protection exception) that would have
occurred in the absence of this erratum. Alternatively, if one of those bits had been 0
and was then set by the XSAVE instruction, a subsequent execution of XRSTOR may
generate a #GP that would not have occurred in the absence of this erratum.
Workaround: It is possible for the BIOS to contain a partial workaround for this erratum that
prevents
compatibility with future processors, software should not set any XSTATE_BV reserved
bits when configuring the header of the XSAVE/XRSTOR save area.
Status: For the steppings affected, see the
AX69. Store Ordering Violation When Using XSAVE
Problem: The store operations done as part of the XSAVE instruction may cause a store ordering
violation with older store operations. The store operations done to save the processor
context in the XSAVE instruction flow, when XSAVE is used to store only the SSE
context, may appear to execute before the completion of older store operations.
37
XSAVE from setting
Summary Tables of Changes.
Summary Tables of Changes.
HEADER.XSTATE_BV reserved
Summary Tables of Changes.
Intel® Xeon® Processor 5400 Series
bits. To ensure
Specification Update