Intel E5405 - Cpu Xeon Quad Core 2.00Ghz Fsb1333Mhz 12M Lga771 Tray Specification page 12

®
Errata Intel Xeon
Stepping Stepping
Number
C-0 E-0
AX26
X X
AX27
X X
AX28
X X
AX29
X X
AX30
X X
AX31
X X
AX32
X X
AX33
X X
AX34
X X
AX35
X X
AX36
X X
AX37
X
AX38
X X
AX39
X X
AX40
X X
AX41
X
AX42
X X
AX43
X X
AX44
X
AX45
X
AX46
X X
AX47
X
AX48
X
AX49
X X
AX50
X X
Intel® Xeon® Processor 5400 Series
Specification Update
®
Processor 5400 Series (Sheet 2 of 3)
Status
(Hardware
Fix?)
Pending x87 FPU Exceptions (#MF) Following STI May Be Serviced Before
No Fix
Higher Priority Interrupts
VERW/VERR/LSL/LAR Instructions May Unexpectedly Update the Last
No Fix
Exception Record (LER) MSR
No Fix INIT Does Not Clear Global Entries in the TLB
No Fix Split Locked Stores May not Trigger the Monitoring Hardware
Programming the Digital Thermal Sensor (DTS) Threshold May Cause
No Fix
Unexpected Thermal Interrupts
Writing Shared Unaligned Data that Crosses a Cache Line without Proper
No Fix
Semaphores or Barriers May Expose a Memory Ordering Issue
General Protection (#GP) Fault May Not Be Signaled on Data Segment Limit
No Fix
Violation above 4-G Limit
No Fix An Asynchronous MCE During a Far Transfer May Corrupt ESP
CPUID Reports Architectural Performance Monitoring Version 2 is Supported,
Plan Fix
When Only Version 1 Capabilities are Available
No Fix B0-B3 Bits in DR6 May Not be Properly Cleared After Code Breakpoint
An xTPR Update Transaction Cycle, if Enabled, May be Issued to the FSB after
No Fix
the Processor has Issued a Stop-Grant Special Cycle
Performance Monitoring Event IA32_FIXED_CTR2 May Not Function Properly
Fixed
when Max Ratio is a Non-Integer Core-to-Bus Ratio
No Fix Instruction Fetch May Cause a Livelock During Snoops of the L1 Data Cache
Use of Memory Aliasing with Inconsistent Memory Type may Cause a System
No Fix
Hang or a Machine Check Exception
A WB Store Following a REP STOS/MOVS or FXSAVE May Lead to Memory-
No Fix
Ordering Violations
VM Exit with Exit Reason "TPR Below Threshold" Can Cause the Blocking by
Fixed MOV/POP SS and Blocking by STI Bits to be Cleared in the Guest
Interruptability-State Field
Using Memory Type Aliasing with Cacheable and WC Memory Types May
No Fix
Lead to Memory Ordering Violations
VM Exit Caused by a SIPI Results in Zero Being Saved to the Guest RIP Field
No Fix
in the VMCS
Fixed NMIs May Not Be Blocked by a VM-Entry Failure
Partial Streaming Load Instruction Sequence May Cause the Processor to
Fixed
Hang
Self/Cross Modifying Code May Not be Detected or May Cause a Machine
Not Fixed
Check Exception
Data TLB Eviction Condition in the Middle of a Cacheline Split Load Operation
Fixed
May Cause the Processor to Hang
Update of Read/Write (R/W) or User/Supervisor (U/S) or Present (P) Bits
Fixed
without TLB Shootdown May Cause Unexpected Processor Behavior
RSM Instruction Execution under Certain Conditions May Cause Processor
Fixed
Hang or Unexpected Instruction Execution Results
No Fix Benign Exception after a Double Fault May Not Cause a Triple Fault Shutdown
ERRATA
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