Intel E5405 - Cpu Xeon Quad Core 2.00Ghz Fsb1333Mhz 12M Lga771 Tray Specification page 35

FREEZE_WHILE_SMM_EN bit in the guest IA32_DEBUGCTL field may be set due to a
VMWRITE
IA32_DEBUGCTL.FREEZE_WHILE_SMM_EN=1
Implication: A VMM will not be able to properly virtualize a guest using the FREEZE_WHILE_SMM
feature.
Workaround: It is possible for the BIOS to contain a workaround for this erratum. Alternatively, the
following software workaround may be used. If a VMM wants to use the
FREEZE_WHILE_SMM feature, it can configure an entry in the VM-entry MSR-load area
for the IA32_DEBUGCTL MSR (1D9H); the value in the entry should set the
FREEZE_WHILE_SMM_EN bit. In addition, the VMM should use VMWRITE to clear the
FREEZE_WHILE_SMM_EN bit in the guest IA32_DEBUGCTL field before every VM entry.
(It is necessary to do this before every VM entry because each VM exit will save that bit
as 1.)
FREEZE_WHILE_SMM_EN bit in the IA32_DEBUGCTL MSR.
Status: For the steppings affected, see the
AX59. VM Entry May Use Wrong Address to Access Virtual-APIC Page
Problem: When XFEATURE_ENABLED_MASK register (XCR0) bit 1 (SSE) is 1, a VM entry
executed with the "use TPR shadow" VM-execution control set to 1 may use the wrong
address to access data on the virtual-APIC page.
Implication: An affected VM entry may exhibit the following behaviors: (1) it may use wrong areas
of the virtual-APIC page to determine whether VM entry fails or whether it induces a VM
exit due to the TPR threshold; or (2) it may clear wrong areas of the virtual-APIC page.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the
AX60. INIT Incorrectly Resets IA32_LSTAR MSR
Problem: In response to an INIT reset initiated either via the INIT# pin or an IPI (Inter Processor
Interrupt), the processor should leave MSR values unchanged. Due to this erratum
IA32_LSTAR MSR (C0000082H), which is used by the iA32e SYSCALL instruction, is
being cleared by an INIT reset.
Implication: If software programs a value in IA32_LSTAR to be used by the SYSCALL instruction and
the processor subsequently receives an INIT reset, the SYSCALL instructions will not
behave as intended. Intel has not observed this erratum in any commercially available
software.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the
AX61. CPUID Instruction May Return Incorrect Brand String
Problem: When a CPUID instruction is executed with EAX = 8000_0002H, 8000_0003H, or
8000_0004H, the returned EAX, EBX, ECX, and/or EDX values may be incorrect.
Implication: When this erratum occurs, the processor may report an incorrect brand string.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the
AX62. Global Instruction TLB Entries May Not be Invalidated on a VM Exit or
VM Entry
Problem: If a VMM is using global page entries (CR4.PGE is enabled and any present page-
directories or page-table entries are marked global), then on a VM entry, the
instruction TLB
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to that field or
This workaround prevents
(Translation Lookaside Buffer)
due to a VM exit
the VM-entry
Summary Tables of Changes.
Summary Tables of Changes.
Summary Tables of Changes.
Summary Tables of Changes.
entries caching global page translations
Intel® Xeon® Processor 5400 Series
that occurs while
failure and sets the
Specification Update