Intel E5405 - Cpu Xeon Quad Core 2.00Ghz Fsb1333Mhz 12M Lga771 Tray Specification page 31

AX45. Partial Streaming Load Instruction Sequence May Cause the Processor
to Hang
Problem: Under some rare conditions, when multiple streaming load instructions (MOVNTDQA)
are mixed with non-streaming loads that split across cache lines, the processor may
hang.
Implication: Under the scenario described above, the processor may hang. Intel has not observed
this erratum with any commercially available software.
Workaround: It is possible for the BIOS to contain a workaround for this erratum. However,
streaming behavior may be re-enabled by setting bit 5 to 1 of the MSR at address 0x21
for software development or testing purposes. If this bit is changed, then a read-
modify-write should be performed to preserve other bits of this MSR. When the
streaming behavior is enabled and using streaming load instructions, always consume
a full cache line worth of data and/or avoid mixing them with non-streaming memory
references. If streaming loads are used to read partial cache lines, and mixed with non-
streaming memory references, use fences to isolate the streaming load operations
from non-streaming memory operations.
Status: For the steppings affected, see the
AX46. Self/Cross Modifying Code May Not be Detected or May Cause a
Machine Check Exception
Problem: If instructions from at least three different ways in the same instruction cache set exist
in the pipeline combined with some rare internal state, self-modifying code (SMC) or
cross-modifying code may not be detected and/or handled.
Implication: An instruction that should be overwritten by another instruction while in the processor
pipeline may not be detected/modified, and could retire without detection. Alternatively
the instruction may cause a Machine Check Exception. Intel has not observed this
erratum with any commercially available software.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the
AX47. Data TLB Eviction Condition in the Middle of a Cacheline Split Load
Operation May Cause the Processor to Hang
Problem: If the TLB translation gets evicted while completing a cacheline split load operation,
under rare scenarios the processor may hang.
Implication: The cacheline split load operation may not be able to complete normally, and the
machine may hang and generate Machine Check Exception. Intel has not observed this
erratum with any commercially available software.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the
AX48. Update of Read/Write (R/W) or User/Supervisor (U/S) or Present (P)
Bits without TLB Shootdown May Cause Unexpected Processor
Behavior
Problem: Updating a page table entry by changing R/W, U/S or P bits, even when transitioning
these bits from 0 to 1, without keeping the affected linear address range coherent with
all TLB (Translation Lookaside Buffers) and paging-structures caches in the processor,
in conjunction with a complex sequence of internal processor micro-architectural
events and store operations, may lead to unexpected processor behavior.
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Summary Tables of Changes.
Summary Tables of Changes.
Summary Tables of Changes.
Intel® Xeon® Processor 5400 Series
Specification Update