Intel E5405 - Cpu Xeon Quad Core 2.00Ghz Fsb1333Mhz 12M Lga771 Tray Specification page 13

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Errata Intel Xeon
Stepping Stepping
Number
C-0 E-0
AX51
X X
AX52
X X
AX53
X X
AX54
X X
AX55
X X
AX56
X X
AX57
X X
AX58
X X
AX59
X
AX60
X
AX61
X
AX62
X X
AX63
X
AX64
X
AX65
X X
AX66
X X
AX67
X
AX68
X
AX69
X
AX70
X X
AX71
X X
AX72
X X
AX73
X X
AX74
X X
AX75
X X
AX76
X X
13
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Processor 5400 Series (Sheet 3 of 3)
Status
(Hardware
Fix?)
No Fix LER MSRs May be Incorrectly Updated
Short Nested Loops That Span Multiple 16-Byte Boundaries May Cause a
No Fix
Machine Check Exception or a System Hang
IA32_MC1_STATUS MSR Bit[60] Does Not Reflect Machine Check Error
No Fix
Reporting Enable Correctly
An Enabled Debug Breakpoint or Single Step Trap May Be Taken after MOV
No Fix SS/POP SS Instruction if it is Followed by an Instruction That Signals a
Floating Point Exception
A VM Exit Due to a Fault While Delivering a Software Interrupt May Save
No Fix
Incorrect Data into the VMCS
A VM Exit Occurring in IA-32e Mode May Not Produce a VMX Abort When
No Fix
Expected
IRET under Certain Conditions May Cause an Unexpected Alignment Check
No Fix
Exception
VM Entry May Fail When Attempting to Set
No Fix
IA32_DEBUGCTL.FREEZE_WHILE_SMM_EN
No Fix VM Entry May Use Wrong Address to Access Virtual-APIC Page
No Fix INIT Incorrectly Resets IA32_LSTAR MSR
No Fix CPUID Instruction May Return Incorrect Brand String
Global Instruction TLB Entries May Not be Invalidated on a VM Exit or VM
No Fix
Entry
No Fix XRSTOR Instruction May Cause Extra Memory Reads
Enabling PECI via the PECI_CTL MSR Does Not Enable PECI and May
No Fix
Corrupt the CPUID Feature Flags
Corruption of CS Segment Register During RSM While Transitioning From
No Fix
Real Mode to Protected Mode
LBR, BTS, BTM May Report a Wrong Address when an Exception/Interrupt
No Fix
Occurs in 64-bit Mode
No Fix The XRSTOR Instruction May Fail to Cause a General-Protection Exception
The XSAVE Instruction May Erroneously Modify Reserved Bits in the
No Fix
XSTATE_BV Field
No Fix Store Ordering Violation When Using XSAVE
No Fix Memory Ordering Violation With Stores/Loads Crossing a Cacheline Boundary
No Fix B0-B3 Bits in DR6 For Non-Enabled Breakpoints May be Incorrectly Set
Unsynchronized Cross-Modifying Code Operations Can Cause Unexpected
Plan Fix
Instruction Execution Results
A Page Fault May Not be Generated When the PS bit is set to "1" in a PML4E
No Fix
or PDPTE
No Fix Not-Present Page Faults May Set the RSVD Flag in the Error Code
No Fix VM Exits Due to "NMI-Window Exiting" May Be Delayed by One Instruction
No Fix A 64-bit Register IP-relative Instruction May Return Unexpected Results
ERRATA
Intel® Xeon® Processor 5400 Series
Specification Update