Intel E5405 - Cpu Xeon Quad Core 2.00Ghz Fsb1333Mhz 12M Lga771 Tray Specification page 24

AX22. Performance Monitoring Events for Retired Instructions (C0H) May
Not Be Accurate
Problem: The INST_RETIRED performance monitor may miscount retired instructions as follows:
• Repeat string and repeat I/O operations are not counted when a hardware interrupt
is received during or after the last iteration of the repeat flow.
• VMLAUNCH and VMRESUME instructions are not counted.
• HLT and MWAIT instructions are not counted. The following instructions, if executed
during HLT or MWAIT events, are also not counted:
a) RSM from a C-state SMI during an MWAIT instruction.
b) RSM from an SMI during a HLT instruction.
Implication: There may be a smaller than expected value in the INST_RETIRED performance
monitoring counter. The extent to which this value is smaller than expected is
determined by the frequency of the above cases.
Workaround: None identified.
Status: For the steppings affected, see the
AX23. Returning to Real Mode from SMM with EFLAGS.VM Set May Result in
Unpredictable System Behavior
Problem: Returning back from SMM mode into real mode while EFLAGS.VM is set in SMRAM may
result in unpredictable system behavior.
Implication: If SMM software changes the values of the EFLAGS.VM in SMRAM, it may result in
unpredictable system behavior. Intel has not observed this behavior in commercially
available software.
Workaround: SMM software should not change the value of EFLAGS.VM in SMRAM.
Status: For the steppings affected, see the
AX24. CMPSB, LODSB, or SCASB in 64-bit Mode with Count Greater or Equal
48
to 2 May Terminate Early
Problem: In 64-bit Mode CMPSB, LODSB, or SCASB executed with a repeat prefix and count
greater than or equal to 2
the following.
• The last iteration not being executed
• Signaling of a canonical limit fault (#GP) on the last iteration
Implication: While in 64-bit mode, with count greater or equal to 2
CMPSB, LODSB or SCASB may terminate without completing the last iteration. Intel
has not observed this erratum with any commercially available software.
Workaround: Do not use repeated string operations with RCX greater than or equal to 2
Status: For the steppings affected, see the
AX25. Writing the Local Vector Table (LVT) when an Interrupt is Pending
May Cause an Unexpected Interrupt
Problem: If a local interrupt is pending when the LVT entry is written, an interrupt may be taken
on the new interrupt vector even if the mask bit is set.
Implication: An interrupt may immediately be generated with the new vector when a LVT entry is
written, even if the new LVT entry has the mask bit set.
Service Routine (ISR) set up for that vector the system will GP fault.
Intel® Xeon® Processor 5400 Series
Specification Update
Summary Tables of
Summary Tables of
48
may terminate early. Early termination may result in one of
Summary Tables of Changes.
Changes.
Changes.
48
, repeat string operations
48
.
If there is no Interrupt
If the ISR does
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