Intel E5405 - Cpu Xeon Quad Core 2.00Ghz Fsb1333Mhz 12M Lga771 Tray Specification page 34

may not be reported in the IDT-vectoring information field. In addition, the
Interruptability-state field may indicate blocking by STI or by MOV SS if such blocking
were in effect before execution of the INTn instruction or before execution of the VM-
entry instruction that injected the software interrupt.
Implication: In general, VMM software that follows the guidelines given in the section "Handling VM
Exits Due to Exceptions" of Intel® 64 and IA-32 Architectures Software Developer's
Manual Volume 3B: System Programming Guide should not be affected. If the erratum
improperly causes indication of blocking by STI or by MOV SS, the ability of a VMM to
inject an interrupt may be delayed by one instruction.
Workaround: VMM software should follow the guidelines given in the section "Handling VM Exits Due
to Exceptions" of Intel® 64 and IA-32 Architectures Software Developer's Manual
Volume 3B: System Programming Guide.
Status: For the steppings affected, see the
AX56. A VM Exit Occurring in IA-32e Mode May Not Produce a VMX Abort
When Expected
Problem: If a VM exit occurs while the processor is in IA-32e mode and the "host address-space
size" VM-exit control is 0, a VMX abort should occur. Due to this erratum, the expected
VMX aborts may not occur and instead the VM Exit will occur normally. The conditions
required to observe this erratum are a VM entry that returns from SMM with the "IA-
32e guest" VM-entry control set to 1 in the SMM VMCS and the "host address-space
size" VM-exit control cleared to 0 in the executive VMCS.
Implication: A VM Exit will occur when a VMX Abort was expected.
Workaround: An SMM VMM should always set the "IA-32e guest" VM-entry control in the SMM VMCS
to be the value that was in the LMA bit (IA32_EFER.LMA.LMA[bit 10]) in the IA32_EFER
MSR (C0000080H) at the time of the last SMM VM exit. If this guideline is followed, that
value will be 1 only if the "host address-space size" VM-exit control is 1 in the executive
VMCS.
Status: For the steppings affected, see the
AX57. IRET under Certain Conditions May Cause an Unexpected Alignment
Check Exception
Problem: In IA-32e mode, it is possible to get an Alignment Check Exception (#AC) on the IRET
instruction even though alignment checks were disabled at the start of the IRET. This
can only occur if the IRET instruction is returning from CPL3 code to CPL3 code. IRETs
from CPL0/1/2 are not affected. This erratum can occur if the EFLAGS value on the
stack has the AC flag set, and the interrupt handler's stack is misaligned. In IA-32e
mode, RSP is aligned to a 16-byte boundary before pushing the stack frame.
Implication: In IA-32e mode, under the conditions given above, an IRET can get a #AC even if
alignment checks are disabled at the start of the IRET. This erratum can only be
observed with a software generated stack frame.
Workaround: Software should not generate misaligned stack frames for use with IRET.
Status: For the steppings affected, see the Summary Tables of Changes.
AX58. VM Entry May Fail When Attempting to Set
IA32_DEBUGCTL.FREEZE_WHILE_SMM_EN
Problem: If bit 14 (FREEZE_WHILE_SMM_EN) is set in the IA32_DEBUGCTL field in the guest-
state area of the VMCS, VM entry may fail as described in Section "VM-Entry Failures
During or After Loading Guest State" of Intel
Developer's Manual Volume 3B: System Programming Guide, Part 2. (The exit reason
will be 80000021H and the exit qualification will be zero.) Note that the
Intel® Xeon® Processor 5400 Series
Specification Update
Summary Tables of Changes.
Summary Tables of Changes.
®
64 and IA-32 Architectures Software
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