Intel E5405 - Cpu Xeon Quad Core 2.00Ghz Fsb1333Mhz 12M Lga771 Tray Specification page 36

of the VMM may not be invalidated. In addition, if a guest is using global page entries,
then on a VM exit, the instruction TLB entries caching global page translations of the
guest may not be invalidated.
Implication: Stale global instruction linear to physical page translations may be used by a VMM after
a VM exit or a guest after a VM entry.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the
AX63. XRSTOR Instruction May Cause Extra Memory Reads
Problem: An XRSTOR instruction will cause non-speculative accesses to XSAVE memory area
locations containing the FCW/FSW and FOP/FTW Floating Point registers even though
the 64-bit restore mask specified in the EDX:EAX register pair does not indicate to
restore the x87 FPU state.
Implication: Page faults, data breakpoint triggers, etc. may occur due to the unexpected non-
speculative accesses to these memory locations.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the
AX64. Enabling PECI via the PECI_CTL MSR Does Not Enable PECI and May
Corrupt the CPUID Feature Flags
Problem: Writing PECI_CTL MSR (Platform Environment Control Interface Control Register) will
not update the PECI_CTL MSR (5A0H), instead it may corrupt the CPUID feature flags.
Implication: Due to this erratum, PECI (Platform Environment Control Interface) will not be enabled
as expected by the software. In addition, due to this erratum, processor features
reported in ECX following execution of leaf 1 of CPUID (EAX=1) may be masked.
Software utilizing CPUID leaf 1 to verify processor capabilities may not work as
intended.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the
AX65. Corruption of CS Segment Register During RSM While Transitioning
From Real Mode to Protected Mode
Problem: During the transition from real mode to protected mode, if an SMI (System
Management Interrupt) occurs between the MOV to CR0 that sets PE (Protection
Enable, bit 0) and the first far JMP, the subsequent RSM (Resume from System
Management Mode) may cause the lower two bits of CS segment register to be
corrupted.
Implication: The corruption of the bottom two bits of the CS segment register will have no impact
unless software explicitly examines the CS segment register between enabling
protected mode and the first far JMP. Intel® 64 and IA-32 Architectures Software
Developer's Manual Volume 3A: System Programming Guide, Part 1, in the section
titled "Switching to Protected Mode" recommends the far JMP immediately follows the
write to CR0 to enable protected mode. Intel has not observed this erratum with any
commercially available software.
Workaround: None Identified
Status: For the steppings affected, see the
Intel® Xeon® Processor 5400 Series
Specification Update
Summary Tables of Changes.
Summary Tables of Changes.
Summary Tables of Changes.
Summary Tables of Changes.
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