Intel E5405 - Cpu Xeon Quad Core 2.00Ghz Fsb1333Mhz 12M Lga771 Tray Specification page 25

not do an End of Interrupt (EOI) the bit for the vector will be left set in the in-service
register and mask all interrupts at the same or lower priority.
Workaround: Any vector programmed into an LVT entry must have an ISR associated with it, even if
that vector was programmed as masked. This ISR routine must do an EOI to clear any
unexpected interrupts that may occur. The ISR associated with the spurious vector
does not generate an EOI, therefore the spurious vector should not be used when
writing the LVT.
Status: For the steppings affected, see the
AX26. Pending x87 FPU Exceptions (#MF) Following STI May Be Serviced
Before Higher Priority Interrupts
Problem: Interrupts that are pending prior to the execution of the STI (Set Interrupt Flag)
instruction are normally serviced immediately after the instruction following the STI. An
exception to this is if the following instruction triggers a #MF. In this situation, the
interrupt should be serviced before the #MF. Because of this erratum, if following STI,
an instruction that triggers a #MF is executed while STPCLK#, Enhanced Intel
SpeedStep Technology transitions or Thermal Monitor events occur, the pending #MF
may be serviced before higher priority interrupts.
Implication: Software may observe #MF being serviced before higher priority interrupts.
Workaround: None identified.
Status: For the steppings affected, see the
AX27. VERW/VERR/LSL/LAR Instructions May Unexpectedly Update the Last
Exception Record (LER) MSR
Problem: The LER MSR may be unexpectedly updated, if the resultant value of the Zero Flag (ZF)
is zero after executing the following instructions
1. VERR (ZF=0 indicates unsuccessful segment read verification)
2. VERW (ZF=0 indicates unsuccessful segment write verification)
3. LAR (ZF=0 indicates unsuccessful access rights load)
4. LSL (ZF=0 indicates unsuccessful segment limit load)
Implication: The value of the LER MSR may be inaccurate if VERW/VERR/LSL/LAR instructions are
executed after the occurrence of an exception.
Workaround: Software exception handlers that rely on the LER MSR value should read the LER MSR
before executing VERW/VERR/LSL/LAR instructions.
Status: For the steppings affected, see the
AX28. INIT Does Not Clear Global Entries in the TLB
Problem: INIT may not flush a TLB entry when:
• The processor is in protected mode with paging enabled and the page global enable
flag is set (PGE bit of CR4 register)
• G bit for the page table entry is set
• TLB entry is present in TLB when INIT occurs
Implication: Software may encounter unexpected page fault or incorrect address translation due to
a TLB entry erroneously left in TLB after INIT.
25
Summary Tables of Changes.
Summary Tables of Changes.
Summary Tables of Changes.
Intel® Xeon® Processor 5400 Series
Specification Update