Intel E5405 - Cpu Xeon Quad Core 2.00Ghz Fsb1333Mhz 12M Lga771 Tray Specification page 19

AX4. Non-Temporal Data Store May be Observed in Wrong Program Order
Problem: When non-temporal data is accessed by multiple read operations in one thread while
another thread performs a cacheable write operation to the same address, the data
stored may be observed in wrong program order (i.e. later load operations may read
older data).
Implication: Software that uses non-temporal data without proper serialization before accessing the
non-temporal data may observe data in wrong program order.
Workaround: Software that conforms to the Intel® 64 and IA-32 Architectures Software Developer's
Manual, Volume 3A, section "Buffering of Write Combining Memory Locations" will
operate correctly.
Status: For the steppings affected, see the
AX5. Page Access Bit May be Set Prior to Signaling a Code Segment Limit
Fault
Problem: If code segment limit is set close to the end of a code page, then due to this erratum
the memory page Access bit (A bit) may be set for the subsequent page prior to
general protection fault on code segment limit.
Implication: When this erratum occurs, a non-accessed page which is present in memory and
follows a page that contains the code segment limit may be tagged as accessed.
Workaround: Erratum can be avoided by placing a guard page (non-present or non-executable page)
as the last page of the segment or after the page that includes the code segment limit.
Status: For the steppings affected, see the
AX6. Updating Code Page Directory Attributes without TLB Invalidation May
Result in Improper Handling of Code #PF
Problem: Code #PF (Page Fault exception) is normally handled in lower priority order relative to
both code #DB (Debug Exception) and code Segment Limit Violation #GP (General
Protection Fault). Due to this erratum, code #PF may be handled incorrectly, if all of the
following conditions are met:
1. A PDE (Page Directory Entry) is modified without invalidating the corresponding
TLB (Translation Look-aside Buffer) entry
2. Code execution transitions to a different code page such that both
3. One of the following simultaneous exception conditions is present following the
code transition
Implication: Software may observe either incorrect processing of code #PF before code Segment
Limit Violation #GP or processing of code #PF in lieu of code #DB.
Workaround: None identified.
Status: For the steppings affected, see the
AX7. Storage of PEBS Record Delayed Following Execution of MOV SS or STI
Problem: When a performance monitoring counter is configured for PEBS (Precise Event Based
Sampling), overflow of the counter results in storage of a PEBS record in the PEBS
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• The target linear address corresponds to the modified PDE
• The PTE (Page Table Entry) for the target linear address has an A
(Accessed) bit that is clear
• Code #DB and code #PF
• Code Segment Limit Violation #GP and code #PF
Summary Tables of Changes.
Summary Tables of Changes.
Summary Tables of Changes.
Intel® Xeon® Processor 5400 Series
Specification Update