Fpga Development Board Introduction - Alinx ARTIX UltraScale+ AXAU15 User Manual

AXAU15 User Manual
1．FPGA Development Board Introduction
Here, we provide a brief functional introduction to the AXAU15 FPGA development
platform.
The entire structure of the development board inherits our consistent design pattern of
core board+extension board. The core board and expansion board are connected by
using high-speed inter board connectors.
The core board is mainly composed of FPGA+1 DDR4+QSPI FLASH, responsible for
high-speed data processing and storage functions of FPGA. The entire system
bandwidth can reach up to 12.5Gb/s (800M * 16bit) by high-speed data reading and
writing between FPGA and a DDR4, with a data bit width of 16 bits; In addition, the
DDR4 has a capacity of up to 8Gbit, meeting the demand for high buffers during data
processing. The FPGA we selected is the XCAU15P chip of the ARTIX UltraScale+series
from XILINX company. The FPGA we have chosen is packaged in FFVB676. The clock
frequency for communication between XCAU15P and DDR4 reaches 1200Mhz, with a
data rate of 2400bps, fully meeting the requirements of high-speed multi-channel data
processing. Also XCAU15P comes with 12 GTH high-speed transceivers, each with a
speed of up to 12.5Gb/s, making it very suitable for fiber optic communication and
PCIe data communication.
The following figure is a schematic diagram of the entire development system
structure:
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