Alinx ARTIX UltraScale+ AXAU15 User Manual page 11

resistance/terminal resistance, line impedance control, and line length control
to ensure the high-speed and stable operation of DDR4.
The hardware connection method between FPGA and DDR4 DRAM is shown in
Figure 2-4-1:
DDR4 DRAM pin assignments：
Signal Name
PL_DDR4_A0
PL_DDR4_A1
PL_DDR4_A2
PL_DDR4_A3
PL_DDR4_A4
PL_DDR4_A5
PL_DDR4_A6
PL_DDR4_A7
PL_DDR4_A8
PL_DDR4_A9
PL_DDR4_A10
PL_DDR4_A11
PL_DDR4_A12
PL_DDR4_A13
PL_DDR4_ACT_B
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FPGA
BANK
66
Address line, control line
Figure 2-4-1 DDR4 DRAM Schematic
FPGA Pin Name
IO_L13N_T2L_N1_GC_QBC_66
IO_L8N_T1L_N3_AD5N_66
IO_L10N_T1U_N7_QBC_AD4N_66
IO_L19N_T3L_N1_DBC_AD9N_66
IO_L8P_T1L_N2_AD5P_66
IO_T3U_N12_66
IO_L17P_T2U_N8_AD10P_66
IO_L16P_T2U_N6_QBC_AD3P_66
IO_L17N_T2U_N9_AD10N_66
IO_L12P_T1U_N10_GC_66
IO_L15P_T2L_N4_AD11P_66
IO_L12N_T1U_N11_GC_66
IO_L16N_T2U_N7_QBC_AD3N_66
IO_L14N_T2L_N3_GC_66
IO_L9P_T1L_N4_AD12P_66
AXAU15 User Manual
Data cable
DDR4
(MT40A512M1
6LY-062EIT)
FPGA Pin No.
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G25
M26
L25
E26
M25
F22
H26
F24
G26
J23
J25
J24
F25
H24
K25