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Alinx ARTIX UltraScale+ AXAU15 User Manual page 12

Fpga development board

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PL_DDR4_BA0
PL_DDR4_BA1
PL_DDR4_BG0
PL_DDR4_CAS_B
PL_DDR4_CKE
PL_DDR4_CLK_N
PL_DDR4_CLK_P
PL_DDR4_CS_B
PL_DDR4_PAR
PL_DDR4_RAS_B
PL_DDR4_OTD
PL_DDR4_WE_B
PL_DDR4_DM0
PL_DDR4_DM1
PL_DDR4_DQ0
PL_DDR4_DQ1
PL_DDR4_DQ2
PL_DDR4_DQ3
PL_DDR4_DQ4
PL_DDR4_DQ5
PL_DDR4_DQ6
PL_DDR4_DQ7
PL_DDR4_DQ8
PL_DDR4_DQ9
PL_DDR4_DQ10
PL_DDR4_DQ11
PL_DDR4_DQ12
PL_DDR4_DQ13
PL_DDR4_DQ14
PL_DDR4_DQ15
PL_DDR4_DQS0_N
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IO_L15N_T2L_N5_AD11N_66
IO_T2U_N12_66
IO_L7P_T1L_N0_QBC_AD13P_66
IO_L18N_T2U_N11_AD2N_66
IO_L7N_T1L_N1_QBC_AD13N_66
IO_L11N_T1U_N9_GC_66
IO_L11P_T1U_N8_GC_66
IO_L14P_T2L_N2_GC_66
IO_L10P_T1U_N6_QBC_AD4P_66
IO_L18P_T2U_N10_AD2P_66
IO_T1U_N12_66
IO_L9N_T1L_N5_AD12N_66
IO_L19P_T3L_N0_DBC_AD9P_66
IO_L1P_T0L_N0_DBC_66
IO_L20P_T3L_N2_AD1P_66
IO_L21N_T3L_N5_AD8N_66
IO_L20N_T3L_N3_AD1N_66
IO_L24N_T3U_N11_66
IO_L21P_T3L_N4_AD8P_66
IO_L23P_T3U_N8_66
IO_L24P_T3U_N10_66
IO_L23N_T3U_N9_66
IO_L2P_T0L_N2_66
IO_L3N_T0L_N5_AD15N_66
IO_L3P_T0L_N4_AD15P_66
IO_L2N_T0L_N3_66
IO_L6P_T0U_N10_AD6P_66
IO_L5N_T0U_N9_AD14N_66
IO_L6N_T0U_N11_AD6N_66
IO_L5P_T0U_N8_AD14P_66
IO_L22N_T3U_N7_DBC_AD0N_66
AXAU15 User Manual
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H21
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L18
F23
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