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Ddr4 - Alinx ARTIX UltraScale+ AXAU15 User Manual

Fpga development board

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Figure 2-3-2 156.25Mhz Active differential crystal oscillator
System Clock pin assignments:
Signal Name
GTH_CLK0_P
GTH_CLK0_N

2.4 DDR4

The ACAU15 core board is equipped with Micron's 8Gbit DDR4 chip, model
MT40A512M16LY-062EIT. The bus width of DDR is a total of 16 bits. The
maximum operating speed of DDR4 SDRAM can reach 1200MHz (data rate
2400Mbps). The DDR4 storage system is directly connected to the memory
interface of the FPGA's BANK 66. The specific configuration of DDR4 SDRAM is
shown in Table 2-4-1.
Bit No.
U2
MT40A512M16LY-062EIT
The hardware design of DDR4 requires strict consideration of signal integrity.
When designing the circuit and PCB, we have fully considered matching
10 / 40
Table 2-4-1 DDR3 SDRAM Configuration
Chip Model
AXAU15 User Manual
FPGA Pin
T7
T6
Capacity
Manufacturer
512M x 16bit
www.alinx.com
micron

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