Fpga Development Board Introduction - Alinx Z19 User Manual

Z19 User Manual
1． FPGA Development Board Introduction
The Z19 MPSoCs is mainly composed of ZU19EG, 4 DDR4, DDR4 SODIMM, eMMC, and 2
QSPI FLASH. Its main chip adopts Xilinx's Zynq UltraScale+ MPSoCs series chip, model
XCZU19EG--2FFVC1760I. The ZU19EG chip can be divided into a Processor System part
(PS) and a Programmable Logic part (PL), and 4 pieces of DDR4 and one 260-pin DDR4
SODIMM slot are attached to the two sides respectively. The capacity of each DDR4 chip
on the PS side is up to 2GB, which enables the ARM system and the FPGA system to
process and store data independently. The 32GB eMMC FLASH memory chip and 2
pieces of 512Mb QSPI FLASH chips on the PS side are used to statically store the MPSoCs'
operating system, file system and user data.
The Z19 MPSoCs is extended with a rich set of peripheral interfaces, including 2 FMC
dual-width interfaces, 1 M.2 SSD interface, 1 PCIE main mode slot, 4 SATA interfaces, 3
pairs of differential SMA interfaces, 1 mini_DP interface, 4 QSFP28 fiber interfaces, 4
USB3.0 interfaces, 2 Gigabit Ethernet interfaces, 3 UART interfaces, 1 TF card slot, 2 CAN
bus interfaces, 2 RS485 interfaces and 1 MIPI camera interface and some key LEDs.
The following is the structure diagram of the whole development system:
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