Omron CP1L CPU UNIT - 06-2007 Operation Manual page 331

Inverter Positioning
System Configuration
Instructions Used
Terminal Allocations
298
Speed Command via Serial Communications
SYSMAC
IN
CP1L
L1 L2/N COM 01 03 05 07 09 11 01 03 05 07 09 11
00 02 04 06 08 10 00 02 04 06 08 10
00 01 02 03 04 06 00 01 03 04 06
COM COM COM COM 05 07 COM 02 COM 05 07
OUT
CP1L
PLS2(887)
■ Error Counter
Error counter 0
Phase B
01
L1 L2/N COM
00 02
Error counter 0
Phase A
■
RS-422A/485 Communications (CP1W-CIF11)
RDA- RDB+ SDA- SDB+
RS-485
communications
(Modbus-RTU)
COMM
CP1W-CIF11
Feedback pulses
Error counter 1
Error counter 1
Phase B
Phase Z
03 05 07 09 11
04 06 08 10
CIO 0
Error counter 1 Error counter 0
Phase A Phase Z
SW
1
2
FG
3
4
5
6
Section 5-3
Inverter
3G3MV
3G3RV
Standard motor
Encoder
01 03 05 07
00 02 04 06 08
CIO 1
ON
09 11
10