4-11 Index Registers - Omron CP1L CPU UNIT - 06-2007 Operation Manual

Index Registers
DM Fixed Allocation
Words for Modbus-RTU
Easy Master

4-11 Index Registers

Indirect Addressing
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(2) If two-word data is accessed from the last address in the DM Area (D9999
for the CP1L-L@D@-@ and D32767 for other CPU Units), the Access Er-
ror Flag (P_AER) will turn ON and the data at D9999 or D32767 will not
be read or written.
The following DM area words are used as command and response storage
areas for the Modbus-RTU Easy Master function.
D32200 to D32299: Serial port 1 on CP1L CPU Unit with M CPU type
D32300 to D32399: Serial port 2 on CP1L CPU Unit with M CPU type and
serial port 1 on CP1L CPU Unit with L CPU type
For use of these areas, refer to 6-3-3 Modbus-RTU Easy Master Function.
The sixteen Index Registers (IR0 to IR15) are used for indirect addressing.
Each Index Register can hold a single PLC memory address, which is the
absolute memory address of a word in I/O memory. Use MOVR(560) to con-
vert a regular data area address to its equivalent PLC memory address and
write that value to the specified Index Register. (Use MOVRW(561) to set the
PLC memory address of a timer/counter PV in an Index Register.)
Note Refer to Appendix E Memory Map for more details on PLC memory
addresses.
When an Index Register is used as an operand with a "," prefix, the instruction
will operate on the word indicated by the PLC memory address in the Index
Register, not the Index Register itself. Basically, the Index Registers are I/O
memory pointers.
• All addresses in I/O memory (except Index Registers, Data Registers, and
Condition Flags) can be specified seamlessly with PLC memory
addresses. It isn't necessary to specify the data area. I/O memory
addresses for IR, DR, and Condition Flags, however, cannot be held.
• In addition to basic indirect addressing, the PLC memory address in an
Index Register can be offset with a constant or Data Register, auto-incre-
mented, or auto-decremented. These functions can be used in loops to
read or write data while incrementing or decrementing the address by one
each time that the instruction is executed.
With the offset and increment/decrement variations, the Index Registers can
be set to base values with MOVR(560) or MOVRW(561) and then modified as
pointers in each instruction.
Set to a base value
with MOVR(560) or
MOVRW(561).
Note It is possible to specify regions outside of I/O memory and generate an Illegal
Access Error when indirectly addressing memory with Index Registers. Refer
to Appendix E Memory Map for details on the limits of PLC memory
addresses.
I/O Memory
Pointer
Section 4-11