Sma Interface - Alinx Z19 User Manual

Zynq ultrascale+ mpsoc development board
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Z19 User Manual

21. SMA Interface

The Z19 development board has three pairs of differential lines, which are drawn
through six SMA interfaces, one pair is clock signal and the other two pairs are data
signals. The differential signal is connected to the IO of the BANK68 (level standard 1.8V
or 1.2V and can be adjusted via hop cap). Figure 21-1 shows the design of SMA
interface.
SMA interface ZYNQ pin assignment:
Signal Name
CLKN_D14
CLKP_E15
DATA0N
DATA0P
DATA1N
www.alinx.com
Figure 21-1: The design of SMA interface
Pin Name
IO_L14N_T2L_N3_GC_68
IO_L14P_T2L_N2_GC_68
IO_L18N_T2U_N11_AD2N_68
IO_L18P_T2U_N10_AD2P_68
IO_L10N_T1U_N7_QBC_AD4N_68
Pin No.
Description
D14
SMA clock Negative
E15
SMA clock Positive
B15
SMA data 0 reception
C15
SMA data 0 reception Positive
SMA data 1 reception
F18
Negative
Negative
68/74

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