Alinx Z19 User Manual page 54

Z19 User Manual
FMC1_SDA
FMC1_SCL
The 60 pairs of differential signals of the FMC2 expansion port are connected to the IO
of the BANK64, 65, 66 of the ZYNQ Ultrascale+ chip, the level standard is 1.8V or 1.2V
(chose by hop cap J88), and the differential signal supports LVDS data communication.
Eight sets of GTH transceiver signals are connected to BANK224 and BANK225. Figure
18-2 shows the diagram of the ZYNQ Ultrascale+ and FMC2 connectors.
FMC1 connector pin assignment :
Signal Name
FMC2_GBTCLK0_M2C_
C_N
FMC2_GBTCLK0_M2C_
C_P
FMC2_GBTCLK1_M2C_
N
FMC2_GBTCLK1_M2C_
P
FMC2_DP4_C2M_N
www.alinx.com
IO_L12N_AD8N_94
IO_L11P_AD9P_94
Figure 18-2: Connection of the FMC1 connector
ZYNQ Pin Name
MGTREFCLK1N_224
MGTREFCLK1P_224
MGTREFCLK0N_224
MGTREFCLK0P_224
MGTHTXN2_224
I2C communication data of FMC1
A4
I2C communication clock of FMC1
B6
Pin No.
FMC2 transceiver reference
AJ9
clock 0, Negative
FMC2 transceiver reference
AJ10
clock 0, Positive
FMC2 transceiver reference
AK11
clock 1, Negative
FMC2 transceiver reference
AK12
clock 1, Positive
FMC2
AU5
transmission 4, Negative
Remarks
transceiver data
54/74