Alinx Z19 User Manual page 10

Z19 User Manual
The ZU19EG chip supports 32-bit or 64-bit DDR4, LPDDR4, DDR3, DDR3L, LPDDR3
memory chips, and has rich high-speed interfaces on the PS side, such as PCIE Gen2,
USB3.0, SATA 3.1, and DisplayPort. It also supports USB2.0, Gigabit Ethernet, SD/SDIO,
I2C, CAN, UART, GPIO and other interfaces. The PL side contains a wealth of
programmable logic unit, DSP and internal RAM. Figure 2-2-1 detailed the Overall Block
Diagram of the ZU19EG chip:
The main parameters of the PS system are as follows:
➢ ARM quad-core Cortex™-A53 processor with a speed of up to 1.3GHz, each CPU
32KB level 1 instruction and data cache, 1MB level 2 cache, shared by 2 CPUs.
➢ ARM dual-core Cortex-R5 processor with a speed of up to 533MHz, each CPU
32KB level 1 instruction and data cache, and 128K tightly coupled memory.
➢ External memory interface: supports 32/64bit DDR4/3/3L, LPDDR4/3 interface.
➢ Static memory interface: supports NAND, 2xQuad-SPI FLASH.
➢ High-speed connection interface, supports PCIe Gen2 x 4, 2 x USB3.0, Sata 3.1,
Display Port, 4 x Tri-mode, Gigabit Ethernet.
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Figure 2-2-1 Overall block diagram of ZYNQ ZU19EG chip
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