Ddr4 Dram - Alinx Z19 User Manual

➢ Common connection interfaces: 2 x USB2.0, 2 x SD/SDIO, 2 x UART, 2 x CAN 2.0B,
2 x I2C, 2 x SPI, 4 x 32b GPIO.
➢ Power management: supports the four-part division of power supply
Full/Low/PL/Battery.
➢ Encryption algorithm: RSA, AES, and SHA.
➢ System monitoring: 10-bit 1Mbps AD sampling for temperature and voltage
detection.
The main parameters of the PL logic part are as follows:
➢ System Logic Cells: 1143K;
➢ CLB flip-flops: 1045K;
➢ CLBLUTs: 523K；
➢ Block RAM: 34.6Mb；
➢ Clock Management Units (CMTs): 11;
➢ DSP Slices: 1968;
➢ GTH 16.3Gb/s transceivers: 44.
The XCZU19EG-2FFVC1760I chip has a speed rating of -2, industrial grade, and is
packaged as FFVC1760.
3． DDR4 DRAM
The Z19 development board is equipped with four Micron 2GB DDR4 chips (model
MT40A1G16KD-062E), which are all mounted on the PS side, comprising a 64-bit data
bus bandwidth and 8GB capacity, while a 260-pin DDR4 SODIMM slot is led on the PL
side. The DDR4 SDRAM on the PS side can run at a maximum speed of 1200MHz
(2400Mbps data rate) and 4 DDR4 memory systems are directly connected to the
memory interface of BANK504 on the PS side. The DDR4 SODIMM slot on the PL side is
connected to the interface of BANK69, 70, 71 on the FPGA. The specific configuration of
DDR4 SDRAM is shown in Table 2-3-1 below.
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Z19 User Manual
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