Pcie D3 Cold State - Quectel EM160R-GL Hardware Design

To ensure the signal integrity of PCIe interface, AC coupling capacitors C5 and C6 should be placed close
to the host on PCB. C1 and C2 have been integrated inside the module, so do not place these two
capacitors on your schematic and PCB.
Comply with the following principles in PCIe interface design to meet PCI Express Base Specification
Revision 4.0.
⚫
Keep the PCIe data and control signals away from sensitive circuits and signals, such as RF, audio,
crystal and oscillator signals.
⚫
Add a capacitor in series on Tx/Rx traces to prevent any DC bias.
⚫
Keep the maximum trace length less than 300 mm.
⚫
Keep the length matching of each differential data pair (Tx/Rx) less than 0.7 mm for PCIe routing
traces.
⚫ Keep the differential impedance of PCIe data trace as 95 Ω ±10 %.
⚫
You must not route PCIe data traces under components or cross them with other traces.
⚫
It is recommended to use a push-pull GPIO to output a low level that approaches 0 V rather than
using a pull-down resistor to get a low level. Otherwise, voltage division may be formed with the
pull-up resistor inside the module, resulting in an uncertain 0 V voltage that could further lead to
unpredictable problems. If host uses a push-pull GPIO to control PERST#, R3 can be not mounted.
3.7.2. PCIe D3
cold
For the laptop platform, module must go through D3
must be kept in high level.
The module enters D3
de-asserted.
EM160R-GL_Hardware_Design
Figure 15: PCIe Interface Reference Circuit (EP Mode)
State
state after PERST# is asserted. The module enters D0 state after PERST# is
cold
before entering D3
hot
LTE-A Module Series
. In D3 state, PERST#
cold hot
37 / 73