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VCC(H)
FULL_CARD_
POWER_OFF#
RESET#
CLKREQ#
Execute AT+CFUN=0,
and the module responds OK
PERST#
PCIE_REFCLK
Module Status
Table 11: Description of Reset Timing
Index
Min.
T1
15 ms
T2
0 ms
T3
250 ms
T4
0 ms
T5
100 ms
100 μs
T6
NOTE
⚫
Module:
1)
When RESET# is kept at low level for 250 ms or more, the module will reset stably.
2)
If PERST# is not pulled down before RESET#, instability in PCIe will be caused. If PERST# is
not pulled high after reset, a system pause will be caused.
⚫
Host:
1)
VCC of the system should supply power continuously and FULL_CARD_POWER_OFF# should
be kept at high level.
EM160R-GL_Hardware_Design
T2
T1
Active
Figure 11: Timing of Resetting the Module
Typ.
Max.
-
-
100 ms
-
-
-
-
-
-
-
-
-
T4
T3
Resetting
Comment
The period from the host PERST# asserting to the its
RESET# asserting.
The period from the host RESET# asserting to its
FULL_CARD_POWER_OFF# asserting.
RESET# should be pulled down for at least 250 ms. An
asserting time less than 250 ms is unreliable.
The period from the host RESET# releasing to its
FULL_CARD_POWER_OFF# releasing.
De-assert PERST# 100 ms after de-asserting
FULL_CARD_POWER_OFF#.
The period during which PCIE_REFCLK_P/M is stable
before PERST# is de-asserted.
LTE-A Module Series
3.7 V
V
≥ 1.19 V
IH
1.8 V
T5
T6
Booting
30 / 73
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