Ant_Config - Quectel EM160R-GL Hardware Design

NOTE
1. Do not design pull-up resistors on the module side in DPR signal design.
2. See document [3] for more details about AT+QCFG="sarcfg".

3.8.6. ANT_CONFIG

EM160R-GL provides an ANT_CONFIG pin for antenna configuration. The signal of the pin is sent from
host system to the module. ANT_CONFIG is an input port which is pulled high internally by default. The
definition of ANT_CONFIG is shown in the table below.
Table 21: Pin Definition of ANT_CONFIG
ANT_CONFIG Level
High/Floating
Low
EM160R-GL_Hardware_Design
Host
GPIO
Figure 20: Reference Design of DPR
DPR 25
Function
Support 2 antennas
Support 4 antennas
LTE-A Module Series
Module
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