Keysight E4428C ESG RF Programming Manual page 207

Data Questionable Frequency Condition Register
The Data Questionable Frequency Condition Register continuously monitors the hardware and
firmware status of the signal generator. Condition registers are read- only.
Table 4-13 Data Questionable Frequency Condition Register Bits
Bit Description
0 Synth. Unlocked. A 1 in this bit position indicates that the synthesizer is unlocked.
1 10 MHz Ref Unlocked. A 1 in this bit position indicates that the 10 MHz reference signal is unlocked.
a 1 GHz Ref Unlocked. A 1 in this bit position indicates that the 1 GHz reference signal is unlocked.
2
b Baseband 1 Unlocked. A 1 in this bit position indicates that the baseband generator is unlocked.
3
4 Unused. This bit is always set to 0.
b Sampler Loop Unlocked. A 1 in this bit position indicates that the sampler loop is unlocked.
5
b YO Loop Unlocked. A 1 in this bit position indicates that the YO loop is unlocked.
6
7−14 Unused. These bits are always set to 0.
15 Always 0.
a
In the N5161A/81A and N5162A/82A these bits are always set to 0.
b
In the N5161A/62A/81A/82A/83A, E4428C, E8257D, E8663B, and the E8663D, this bit is always set to 0.
Table 4-14 Data Questionable Frequency Condition Register Bits
Bit Description
0 Synth. Unlocked. A 1 in this bit position indicates that the synthesizer is unlocked.
1 10 MHz Ref Unlocked. A 1 in this bit position indicates that the 10 MHz reference signal is unlocked.
2 1 GHz Ref Unlocked. A 1 in this bit position indicates that the 1 GHz reference signal is unlocked.
Unused. This bit is always set to 0.
3
4 Unused. This bit is always set to 0.
5 Sampler Loop Unlocked. A 1 in this bit position indicates that the sampler loop is unlocked.
6–14 Unused. These bits are always set to 0.
15 Always 0.
Query:
STATus:QUEStionable:FREQuency:CONDition?
Response: The decimal sum of the bits set to 1.
Keysight Signal Generators Programming Guide
Programming the Status Register System
Status Groups
199