Keysight E4428C ESG RF Programming Manual page 200

Programming the Status Register System
Status Groups
Table 4-10 Data Questionable Condition Register Bits
Bit Description
0, 1, 2 Unused. These bits are always set to 0.
3 Power (summary). This is a summary bit taken from the QUEStionable:POWer register. A 1 in this bit position
indicates that one of the following may have happened: The ALC (Automatic Leveling Control) is unable to
maintain a leveled RF output power (i.e., ALC is UNLEVELED), the reverse power protection circuit has been
tripped. See the
4 Temperature (OVEN COLD). A 1 in this bit position indicates that the internal reference oscillator (reference
oven) is cold.
5
Frequency (summary). This is a summary bit taken from the QUEStionable:FREQuency register. A 1 in this bit
position indicates that one of the following may have happened: synthesizer PLL unlocked, 10 MHz reference
VCO PLL unlocked, 1 GHz reference unlocked, sampler, YO loop unlocked or baseband 1 unlocked. For more
information, see the
6 Unused. This bit is always set to 0.
7 Modulation (summary). This is a summary bit taken from the QUEStionable:MODulation register. A 1 in this
bit position indicates that one of the following may have happened: modulation source 1 underrange,
modulation source 1 overrange, modulation source 2 underrange, modulation source 2 overrange, or modulation
uncalibrated. See the
information.
8 Calibration (summary). This is a summary bit taken from the QUEStionable:CALibration register. A 1 in this
bit position indicates that an error has occurred in the DCFM/DCΦM zero calibration. See the
Questionable Calibration Status Group" on page 205
9 Self Test. A 1 in this bit position indicates that a self- test has failed during power- up. Reset this bit by cycling
the signal generator's line power. *CLS will not clear this bit.
10–14 Unused. These bits are always set to 0.
15 Always 0.
Query:
STATus:QUEStionable:CONDition?
Response: The decimal sum of the bits set to 1
Example: The decimal value 520 is returned. The decimal sum = 512 (bit 9) + 8 (bit 3).
Data Questionable Transition Filters (negative and positive)
The Data Questionable Transition Filters specify which type of bit state changes in the condition
register set corresponding bits in the event register. Changes can be positive (0 to 1) or negative (1
to 0).
Commands:
192
"Data Questionable Power Status Group" on page 194
"Data Questionable Frequency Status Group" on page 198
"Data Questionable Modulation Status Group" on page 202
STATus:QUEStionable:NTRansition <value> (negative transition), or
STATus:QUEStionable:PTRansition <value> (positive transition), where
<value> is the sum of the decimal values of the bits you want to enable.
for more information.
.
for more information.
Keysight Signal Generators Programming Guide
for more
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