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NXP Semiconductors
Table 9. CAN and LIN connectors (J16/J20)
Schematic label
Signal name
J16-1
CANH
J16-2
CANL
J16-3
GND
J20-1
LIN
J20-2
GND
4.4.8 Debug and OTP configuration (J30/SW10/SW12)
Debug mode is active when DEBUG pin (Pin 15) is set to 5 V. See
Watchdog and sets the CAN and LIN transceivers active by default.
OTP mode is active when DEBUG pin is set to 8 V. Once in OTP mode, specific keys are necessary to enter
Test mode. See
Section
J30, SW10, and SW12 offer an onboard solution to set the necessary hardware context for Debug mode and
Test mode entry.
Figure 5. Debug and OTP enablement
Table 10. Debug and OTP configuration (J30/SW10/SW12)
Schematic label
J30-1-2
SW10-1 (OFF)
SW10-2 (ON)
SW12-1 (OFF)
SW12-2 (ON)
UM11879
User manual
Description
CAN bus high.
CAN bus low.
Ground.
LIN bus.
Ground.
7.3.2, or OTP programming process.
5.0 V USB
OTP 8 V
generation
SW10
Signal name
DBG_OTP_EN
Open switch
OTP_DCDC_EN
Open switch
OTP_EN
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 25 September 2023
Section
DBG 5 V
OTP 8 V
SW12
1
2
J30
Description
Jumper ON enables DBG or OTP mode depending on SW10 and
SW12 status.
DC-DC disabled, no 8 V OTP generation.
DC-DC enabled for 8 V OTP generation.
OTP mode is disabled.
OTP mode is enabled if OTP DC-DC is ON. Debug mode is
enabled if OTP DC-DC is OFF.
UM11879
KITFS23LDOEVM evaluation board
7.3.1. Debug mode disables the
VBOS
FS23
DEBUG
100 kΩ
aaa-049444
© 2023 NXP B.V. All rights reserved.
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