Logic Diagram; Input And Output Signals - ABB REL 501-C1 2.5 Technical Reference Manual

3.4
3.5
Time delayed residual overcurrent protection
(TEF)

Logic diagram

TEF--BLKTR
TEF--BC
Operation = ON
Def/NI/VI/EI/LOG
IMin
3Io
&
IN>
20%
±Σ
2fn
50ms
TEF--BLOCK
t
Option: Directional check
Direction
= Directional
EF3IoSTD
3Iox
2fn
cos (φ-65)
3Uo
Figure 59: Simplified logic diagram for the residual overcurrent protection

Input and output signals

Table 119: Input signals for the TEF (TEF--) function block
Signal
BLOCK
BLKTR
BC
Path in local HMI: ServiceReport/Functions/EarthFault/TimeDelayEF/FuncOutputs
1000ms
t
300ms
t
&
3Io>
EFCh
k
&
tMin
t
&
100% FORW ARD
60% REVERSE
0.01Un
Description
Block of function
Block of trip
Information on breaker position, or on breaker closing command
&
t1
&
>1
t
&
& &
&
&
Chapter 5
Current
TEF--TRSOTF
TEF--TRIP
>1
TEF--START
TEF--STFW
TEF--STRV
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