Functional Block Diagram - Analog Devices AD9776 Instruction Manual

FUNCTIONAL BLOCK DIAGRAM

SYNC_O DELAY LINE
SYNC_I
DELAY LINE
DATACLK_OUT
DATA
ASSEMBLER
P1D(15:0)
I LATCH
Q LATCH
P2D(15:0)
CLOCK GENERATION/DISTRIBUTION
2× 2× 2×
2× 2× 2×
DIGITAL CONTROLLER
SERIAL
POWER-ON
PERIPHERAL
RESET
INTERFACE
Figure 1.
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SYNC
n ×
f
/8 COMPLEX
DAC
n = 1 TO 7 MODULATOR
SYNC
10
10
10
10
AD9776/AD9778/AD9779
CLOCK
MULTIPLIER
2×/4×/8×
1
16-BIT
IDAC
16-BIT
QDAC
1
GAIN
GAIN
REFERENCE
AND BIAS
GAIN
GAIN
CLK+
CLK–
IOUT1_P
IOUT1_N
IOUT2_P
IOUT2_N
VREF
RSET
AUX1_P
AUX1_N
AUX2_P
AUX2_N