Spi Register Map - Analog Devices AD9776 Instruction Manual

Dual, 12-/14-/16-bit, 1.0 gsps d/a converter
Table of Contents

Advertisement

SPI REGISTER MAP

Table 10.
Register
Name
Address
Bit 7
Comm
0x00 00
SDIO
Bidirectional
Digital
0x01 01
Filter Interpolation Factor <1:0>
Control
0x02 02
Data Format
Sync
0x03 03
Data Clock Delay Mode <1:0>
Control
0x04 04
0x05 05
0x06 06
0x07 07
Sync Receiver
Enable
PLL Control 0x08 08
0x09 09
PLL Enable
Misc
0x0A 10
PLL Control Voltage Range <2:0> (Read Only)
Control
I DAC
0x0B 11
Control
0x0C 12
I DAC Sleep
Register
Aux DAC1
0x0D 13
Control
Register
0x0E 14
Auxiliary DAC1
Q DAC
0x0F 15
Control
Register
0x10 16
Q DAC Sleep
Aux DAC2
0x11 17
Control
Register
0x12 18
Auxiliary DAC2
0x13
19 to
to
24
0x18
Interrupt
0x19 25
Register
0x1A
26 to
to
31
0x1F
Bit 6
Bit 5
LSB/MSB First
Software
Reset
Dual/Interleaved
Real Mode
Data Bus Mode
Data Clock Divide Ratio <1:0>
Data Clock Delay <3:0>
Sync Out Delay <3:0>
Sync Input Delay <3:0>
Sync Driver
Sync
Enable
Triggering
Edge
PLL Band Select <5:0>
PLL VCO Divider Ratio <1:0>
I DAC Power
Down
Auxiliary DAC1
Auxiliary DAC1
Sign
Current
Power-Down
Direction
Q DAC Power-
Down
Auxiliary DAC2
Auxiliary DAC2
Sign
Current
Power-Down
Direction
Sync Delay IRQ
Bit 4
Bit 3
Power-Down
Auto Power-
Mode
Down Enable
Filter Modulation Mode <3:0>
Data Clock
Inverse Sinc
Delay Enable
Enable
Output Sync Pulse Divide <2:0>
Input Sync Pulse Frequency Ratio <2:0> Sync Input
Input Sync Pulse Timing Error Tolerance <3:0>
DAC Clock Offset <4:0>
PLL Loop Divide Ratio <1:0> PLL Bias Setting <2:0>
PLL Loop Bandwidth Adjustment <4:0>
I DAC Gain Adjustment<7:0>
Auxiliary DAC1 Data <7:0>
Q DAC Gain Adjustment <7;0>
Auxiliary DAC2 Data <7:0>
Reserved
Reserved
Rev. 0 | Page 25 of 56
AD9776/AD9778/AD9779
Bit 2
Bit 1
Bit 0
PLL Lock
Indicator
(Read Only)
Zero
Stuffing
Enable
DATACLK
TxEnable
Q First
Invert
Invert
Reserved
Sync Out
Delay <4>
Delay <4>
PLL VCO AGC Gain
<1:0>
I DAC Gain Adjustment
<9:8>
Auxiliary DAC1 Data
<9:8>
Q DAC Gain Adjustment
<9:8>
Auxiliary DAC2 Data
<9:8>
Sync Delay
Internal
IRQ Enable
Sync
Loopback
Def.
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0xCF
0x37
0x38
0xF9
0x01
0x00
0x00
0xF9
0x01
0x00
0x00
0x00

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the AD9776 and is the answer not in the manual?

Questions and answers

This manual is also suitable for:

Ad9778Ad9779

Table of Contents