Functional Block Diagram - Analog Devices AD9776A Manual

AD9776A/AD9778A/AD9779A
DELAY
SYNC_O
LINE
SYNC_I
DELAY
DATACLK
LINE
DATA
ASSEMBLER
I
P1D[15:0]
LATCH
Q
LATCH
P2D[15:0]
AD9779A

FUNCTIONAL BLOCK DIAGRAM

CLOCK GENERATION/DISTRIBUTION
2× 2× 2×
2× 2× 2×
DIGITAL CONTROLLER
SERIAL
POWER-ON
PERIPHERAL
RESET
INTERFACE
Figure 2. AD9779A Functional Block Diagram
Rev. B | Page 4 of 56
SINC^-1
f
n × /8
DAC
n = 0, 1, 2 ... 7
SINC^-1
10
10
10
10
CLOCK
MULTIPLIER
2×/4×/8×
16-BIT
I DAC
16-BIT
Q DAC
GAIN
GAIN
GAIN
GAIN
REFCLK+
REFCLK–
OUT1_P
OUT1_N
OUT2_P
OUT2_N
VREF
I120
AUX1_P
AUX1_N
AUX2_P
AUX2_N